MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 1663

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

26.4.2 ENET MAC Interrupt Mask Register (HW_ENET_MAC_EIMR)
Address:
Re-
26.4.3 ENET MAC Receive Descriptor Active Register
The Receive Descriptor Active Register (RDAR) is a command register, written by the
user, indicating the receive descriptor ring is updated (empty receive buffers have been
produced by the driver with the empty bit set)
Whenever the register is written, the RDAR bit is set. This is independent of the data actually
written by the user. When set, the uDMA polls the receive descriptor ring and processes
receive frames (provided ether_en is also set). Once the uDMA polls a receive descriptor
whose empty bit is not set, the uDMA clears the RDAR bit and ceases receive descriptor
ring polling until the user sets the bit again, signifying that additional descriptors are placed
into the receive descriptor ring. The RDAR registers are cleared at reset and when ether_en
transitions from asserted to de-asserted or when the ecr_reset is set.
Freescale Semiconductor, Inc.
set
Bit
W
R
31
0
EIMR (bit define is same with EIR register)
30
0
29
0
(HW_ENET_MAC_RDAR)
HW_ENET_MAC_EIMR
28
0
27
0
26
31 0
0
Field
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
25
0
24
0
HW_ENET_MAC_EIMR field descriptions
23
0
22
0
800F_0000h base + 8h offset = 800F_0008h
21
0
EIMR (bit define is same with EIR register)
20
0
19
0
Each bit corresponds to an interrupt source defined by the EIR register.
The corresponding EIMR bit determines whether an interrupt condition
can generate an interrupt. At every processor clock, the EIR samples the
signal generated by the interrupting source. The corresponding EIR bit
reflects the state of the interrupt signal even if the corresponding EIMR
bit is not set.
18
0
• 0 The corresponding interrupt source is masked.
• 1 The corresponding interrupt source is not masked (i.e. interrupt
17
0
is enabled).
16
0
15
0
14
0
13
0
12
0
11
0
Description
10
Chapter 26 Ethernet Controller (ENET)
0
0
9
0
8
0
7
0
6
0
5
0
4
3
0
0
2
0
1
1663
0
0