MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 130

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MCIMX286CVM4B

Manufacturer Part Number
MCIMX286CVM4B
Description
IC MPU I.MX286 289MAPBGA
Manufacturer
Freescale Semiconductor
Series
i.MX28r

Specifications of MCIMX286CVM4B

Core Processor
ARM9
Core Size
32-Bit
Speed
454MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
Peripherals
DMA, I²S, LCD, POR, PWM, WDT
Program Memory Size
128KB (32K x 32)
Program Memory Type
Mask ROM
Ram Size
32K x 32
Voltage - Supply (vcc/vdd)
1.25 V ~ 5.25 V
Data Converters
A/D 17x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
289-LFBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of I /o
-
Eeprom Size
-
Lead Free Status / Rohs Status
Compliant
Operation
5.2 Operation
Within an individual interrupt request line (IRQ only), the ICOLL offers four-level priority
(above base level) for each of its interrupt sources. Preemption of a lower priority interrupt
by a higher priority is supported (interrupt nesting). Interrupts assigned to the same level
are serviced in a strict linear priority order within level from lowest to highest interrupt
source bit number. FIQ interrupts are neither prioritized nor vectorized. All the interrupt
lines can be configured as a FIQ. If more than one is routed to the FIQ, then they must be
discriminated by a software. It is highly recommended to reserve FIQ assignment to time
critical events such as voltage brownouts or timers.
For a single interrupt source bit, there is an enable bit that gates it to the priority logic
(HW_ICOLL_INTERRUPTn[ENABLE]). A software interrupt bit per source bit can be
used to force an interrupt at the appropriate priority level directed to the corresponding
vector address. Each source can be applied to one of the four interrupt levels.
130
HW_ICOLL_INTERRUPT33[SOFTIRQ]
HW_ICOLL_INTERRUPT33[ENABLE]
Figure 5-2. Interrupt Collector IRQ/FIQ Logic for Source 33
HW_ICOLL_INTERRUPT33[ENFIQ]
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
32
63
.
.
.
HW_ICOLL_INTERRUPT33[PRIORITY]
(Vector Table Base Addr )
HW_ICOLL_VBASE
Other sources
1:4
Freescale Semiconductor, Inc.
IRQ
FIQ
APBH
ARM
926

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