MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 367

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

6.5.4 AHB to APBH Bridge Channel Register
The APBH CHANNEL CTRL provides reset/freeze control of each DMA channel.
HW_APBH_CHANNEL_CTRL: 0x030
HW_APBH_CHANNEL_CTRL_SET: 0x034
HW_APBH_CHANNEL_CTRL_CLR: 0x038
HW_APBH_CHANNEL_CTRL_TOG: 0x03C
This register contains individual channel reset/freeze bits.
Address:
Re-
Freescale Semiconductor, Inc.
set
Bit
W
R
CH5_ERROR_
CH4_ERROR_
CH3_ERROR_
CH2_ERROR_
CH1_ERROR_
CH0_ERROR_
31
0
Field
IRQ
IRQ
IRQ
IRQ
IRQ
IRQ
30
5
4
3
2
1
0
0
(HW_APBH_CHANNEL_CTRL)
29
0
HW_APBH_CHANNEL_CTRL
28
0
Error interrupt status bit for APBX DMA Channel 5. This sticky bit is set by DMA hardware and reset by
software. It is ORed with the corresponding cmdcmplt irq to generate an irq to ARM.
Error interrupt status bit for APBX DMA Channel 4. This sticky bit is set by DMA hardware and reset by
software. It is ORed with the corresponding cmdcmplt irq to generate an irq to ARM.
Error interrupt status bit for APBX DMA Channel 3. This sticky bit is set by DMA hardware and reset by
software. It is ORed with the corresponding cmdcmplt irq to generate an irq to ARM.
Error interrupt status bit for APBX DMA Channel 2. This sticky bit is set by DMA hardware and reset by
software. It is ORed with the corresponding cmdcmplt irq to generate an irq to ARM.
Error interrupt status bit for APBX DMA Channel 1. This sticky bit is set by DMA hardware and reset by
software. It is ORed with the corresponding cmdcmplt irq to generate an irq to ARM.
Error interrupt status bit for APBX DMA Channel 0. This sticky bit is set by DMA hardware and reset by
software. It is ORed with the corresponding cmdcmplt irq to generate an irq to ARM.
27
0
26
0
RESET_CHANNEL
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
25
0
HW_APBH_CTRL2 field descriptions (continued)
24
0
23
0
22
0
21
0
20
0
8000_4000h base + 30h offset = 8000_4030h
19
0
18
0
17
0
Chapter 6 AHB-to-APBH Bridge with DMA (APBH-Bridge-DMA)
16
0
15
0
Description
14
0
13
0
12
0
11
0
10
FREEZE_CHANNEL
0
0
9
0
8
0
7
0
6
0
5
0
4
3
0
0
2
0
1
367
0
0