MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 1332

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

Programmable Registers
1332
WAIT_FOR_CMD
WAIT_FOR_IRQ
IGNORE_CRC
BUS_WIDTH
DATA_XFER
SDIO_IRQ_
LOCK_CS
CHECK
READ
23 22
Field
28
27
26
25
24
21
20
In SD/MMC mode: SDIO IRQ: 1= Enable checking for SDIO Card IRQ.
In SPI mode: This affects the SSn output.
When set to 1, SSn will be asserted throughout the current command. SSn will remain asserted after the
command if IGNORE_CRC = 0.
SSn will deassert at the end of the next command that has IGNORE_CRC = 1.
In SD/MMC mode:
0= Look for a CRC status token from the card on DATA0 after a block write.
1= Ignore the CRC status response on DATA0 after a write operation.
Note that the SD/MMC function should be used when performing MMC BUSTEST_W operation.
Ignore CRC - In SD/MMC.
In SPI/SSI modes: When set to 1, deassert the chip select (SSn) pin after the command is executed.
Read Mode - When this and DATA_XFER are set, the SSP will read data from the device. If this is not set,
then the SSP will write data to the device.
Data Transfer Mode - When set, transfer XFER_COUNT bytes of data. When not set, the SSP will not
transfer any data (command or Wait for IRQ only).
Data Bus Width - SD/MMC modes supports all widths, SSI mode supports only 1-bit bus width.
In SPI mode 1, 2, and 4-bit bus widths are supported. In SPI mode the Data Bus Width field is redefined: 0
means 1-bit; 1 means 2-bit; 2 means 4-bit.
0x0
0x1
0x2
Wait for IRQ
In SD/MMC mode this signal means wait for MMC ready before sending command. (MMC is busy when
databit0 is low.)
In SPI/SSI mode this bit and WAIT_FOR_CMD bit select which SSn output to assert:
(WAIT_FOR_IRQ,WAIT_FOR_CMD) =
b00: SSn0 will assert during access (SSn2, SSn1 inactive); b01: SSn1 will assert during access (SSn2,
SSn0 inactive); b10: SSn2 will assert during access (SSn1, SSn0 inactive).
Wait for Data Done - SD/MMC - 0: Send commands immediately after they are written.
1: Wait to send command until after the CRC-checking phase of a data transfer has completed successfully.
This delays sending a command until a block of data is transferred. This can be used to send a STOP
command during an SD/MMC multi-block read.
In SD/MMC mode this signal means wait for MMC ready before sending command. (MMC is busy when
databit0 is low.)
In SPI/SSI mode this bit and WAIT_FOR_IRQ bit select which SSn output to assert:
(WAIT_FOR_IRQ,WAIT_FOR_CMD) =
b00: SSn0 will assert during access (SSn2, SSn1 inactive); b01: SSn1 will assert during access (SSn2,
SSn0 inactive); b10: SSn2 will assert during access (SSn1, SSn0 inactive).
ONE_BIT — SD/MMC data bus is 1-bit wide
FOUR_BIT — SD/MMC data bus is 4-bits wide
EIGHT_BIT — SD/MMC data bus is 8-bits wide
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
HW_SSP_CTRL0 field descriptions (continued)
Description
Freescale Semiconductor, Inc.