MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 149

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

5.4.2 Interrupt Collector Level Acknowledge Register
The Interrupt Collector Level Acknowledge Register is used by software to indicate the
completion of an interrupt on a specific level.
This register is written to advance the ICOLL internal IRQ state machine. It advances from
an in-service on a level state to the next pending interrupt level or to the idle state. This
register is written at the very end of an interrupt service routine. If nesting is used then the
CPU IRQ must be turned on before writing to this register to avoid a race condition in the
CPU interrupt hardware. WARNING: the value written to the levelack register is decoded
not binary, i.e. 8, 4, 2, 1.
EXAMPLE
Address:
Re-
Freescale Semiconductor, Inc.
Reset
set
Bit
W
R
IRQVECTOR
HW_ICOLL_LEVELACK_WR(HW_ICOLL_LEVELACK__LEVEL3);
Bit
W
31
RSRVD1
RSRVD1
0
R
Field
31 2
Field
31 4
1 0
30
0
15
0
(HW_ICOLL_LEVELACK)
29
0
HW_ICOLL_LEVELACK
28
0
14
0
This register presents the vector address for the interrupt currently active on the CPU IRQ input. Writing to
this register notifies the interrupt collector that the interrupt service routine for the current interrupt has been
entered (alternatively when ARM_RSE_MODE is set, reading this register is required).
Always write zeroes to this field.
Any value can be written to this bitfield. Writes are ignored.
27
0
26
0
13
0
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
25
0
24
0
12
0
HW_ICOLL_LEVELACK field descriptions
HW_ICOLL_VECTOR field descriptions
23
0
22
0
11
0
8000_0000h base + 10h offset = 8000_0010h
21
0
20
10
0
0
IRQVECTOR[15:2]
19
0
RSRVD1
18
0
0
9
17
0
16
0
0
8
15
0
Description
Description
14
0
7
0
13
0
0
12
6
0
11
0
5
0
10
0
Chapter 5 Interrupt Collector (ICOLL)
0
9
4
0
0
8
0
7
0
3
0
6
0
5
0
2
0
4
IRQLEVELACK
3
0
RSRVD1
0
1
0
2
0
1
0
0
149
0
0