MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 891

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

10.8.27 System Reset Control Register (HW_CLKCTRL_RESET)
The RESET control register provides control for software reset and enable/disable reset
control in analog.
EXAMPLE
HW_CLKCTRL_RESET_WR(BF_CLKCTRL_RESET_ALL(1));
Address:
Freescale Semiconductor, Inc.
Reset
Reset
RESET_ENABLE
BYPASS_SAIF1
BYPASS_SAIF0
WDOG_POR_
EXTERNAL_
Bit
Bit
W
W
DISABLE
R
R
RSRVD
Field
Field
31 6
1
0
5
4
31
15
0
0
HW_CLKCTRL_RESET
30
14
0
0
Always set to zero (0) for functional operation. Bypass is only used for POR and SAIF1 divider configuration.
Always set to zero (0) for functional operation Bypass is only used for POR and SAIF0 divider configuration.
Always set to zero (0).
Analog Reset Control. Setting this bit to a logic one will disable the function that watchdog perform a POR.
Then watchdog will function same with software reset HW_CLKCTRL_RESET.CHIP. Setting this bit to a
logic zero, watchdog_reset will trigger a POR. This bit's reset value reflects OTP fuse
WDOG_PERFORM_POR.
Analog Reset Control. Setting this bit to a logic one will enable the external pin reset control logic.
HW_CLKCTRL_CLKSEQ field descriptions (continued)
29
13
0
0
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
28
12
0
0
HW_CLKCTRL_RESET field descriptions
RSRVD[15:6]
27
11
0
0
8004_0000h base + 1E0h offset = 8004_01E0h
26
10
0
0
25
0
0
9
RSRVD[31:16]
24
0
0
8
Description
Description
Chapter 10 Clock Generation and Control (CLKCTRL)
23
0
0
7
22
0
0
6
21
0
5
0
20
0
4
1
19
0
0
3
18
0
0
2
CHIP
17
0
1
1
DIG
16
0
0
0
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