MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 1656

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

Programmable Registers
1656
800F_00EC
800F_00C4
800F_00E4
800F_00E8
800F_011C
800F_014C
800F_019C
800F_01A0
800F_0064
800F_0084
800F_0118
800F_0120
800F_0124
800F_0144
800F_0150
800F_0180
800F_0184
800F_0188
800F_0190
800F_0194
800F_0198
Absolute
address
(hex)
ENET MAC MIB Control/Status Register
(HW_ENET_MAC_MIBC)
ENET MAC Receive Control Register (HW_ENET_MAC_RCR)
ENET MAC Transmit Control Register
(HW_ENET_MAC_TCR)
ENET MAC Physical Address Lower Register
(HW_ENET_MAC_PALR)
ENET MAC Physical Address Upper Register
(HW_ENET_MAC_PAUR)
ENET MAC Opcode/Pause Duration Register
(HW_ENET_MAC_OPD)
ENET MAC Descriptor Individual Upper Address Register
(HW_ENET_MAC_IAUR)
ENET MAC Descriptor Individual Lower Address Register
(HW_ENET_MAC_IALR)
ENET MAC Descriptor Group Upper Address Register
(HW_ENET_MAC_GAUR)
ENET MAC Descriptor Group Lower Address Register
(HW_ENET_MAC_GALR)
ENET MAC Transmit FIFO Watermark and Store and Forward
Control Register (HW_ENET_MAC_TFW_SFCR)
ENET MAC FIFO Receive Bound Register
(HW_ENET_MAC_FRBR)
ENET MAC FIFO Receive FIFO Start Register
(HW_ENET_MAC_FRSR)
ENET MAC Pointer to Receive Descriptor Ring Register
(HW_ENET_MAC_ERDSR)
ENET MAC Pointer to Transmit Descriptor Ring Register
(HW_ENET_MAC_ETDSR)
ENET MAC Maximum Receive Buffer Size Register
(HW_ENET_MAC_EMRBR)
ENET MAC Receive FIFO Section Full Threshold Register
(HW_ENET_MAC_RX_SECTION_FULL)
ENET MAC Receive FIFO Section Empty Threshold Register
(HW_ENET_MAC_RX_SECTION_EMPTY)
ENET MAC Receive FIFO Almost Empty Threshold Register
(HW_ENET_MAC_RX_ALMOST_EMPTY)
ENET MAC Receive FIFO Almost Full Thresholdt Register
(HW_ENET_MAC_RX_ALMOST_FULL)
ENET MAC Transmit FIFO Section Empty Threshold Register
(HW_ENET_MAC_TX_SECTION_EMPTY)
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
HW_ENET memory map (continued)
Register name
(in bits)
Width
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Freescale Semiconductor, Inc.
C000_0000h
05EE_0001h
Reset value
0000_0000h
0000_0000h
0000_8808h
0001_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0600h
0000_0500h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0004h
0000_0004h
0000_0000h
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