MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 1317

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

each data transfer to enable the serial peripheral data write. On completion of the continuous
transfer, the SSn pin is returned to its idle state one SSP_SCK period after the last bit has
been captured.
17.5.4 Motorola SPI Format with Polarity=0, Phase=1
The transfer signal sequence for Motorola SPI format with POLARITY=0 and PHASE=1
is shown in
In this configuration, during idle periods:
If the SSP is enabled and there is valid data within the FIFO, the start of the transmission
is signified by the SSn master signal being low. After a further one-half SSP_SCK period,
both master and slave valid data are enabled with a rising-edge transition.
Data is then captured on the falling edges and propagated on the rising edges of the SSP_SCK
signal.
In the case of a single word transfer, after all bits have been transferred, the SSn line is
returned to its idle high state one SSP_SCK period after the last bit has been captured.
For continuous back-to-back transfers, SSPFSOUT (the SSn pin in master mode) is held
low between successive data words and termination is the same as that of a single word
transfer.
Freescale Semiconductor, Inc.
Figure 17-4. Motorola SPI Frame Format (Continuous Transfer) with POLARITY=0 and
• The SSP_SCK signal is forced low.
• SSn is forced high.
• The Transmit data line MOSI is arbitrarily forced low.
• When the SSP is configured as a master, the SSP_SCK pad is an output.
• When the SSP is configured as a slave, the SSP_SCK is an input.
Figure
SSP_SCK
MISO
MOSI
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
17-4, which covers both single and continuous transfers.
SSn
Q
MSB
MSB
PHASE=1
4 to 16 bits
Chapter 17 Synchronous Serial Ports (SSP)
LSB
LSB
Q
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