MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 2274

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

Programmable Registers
38.5.2 LRADC Control Register 1 (HW_LRADC_CTRL1)
The LRADC Control Register 1 provides overall control of the eight low resolution analog
to digital converters.
HW_LRADC_CTRL1: 0x010
HW_LRADC_CTRL1_SET: 0x014
HW_LRADC_CTRL1_CLR: 0x018
HW_LRADC_CTRL1_TOG: 0x01C
The LRADC control register 1 provides control over the shared eight channel LRADC
converter. It allows software to independently schedule conversion cycles on any number
of any size subsets of the eight channels. In addition it allows software to manage the
interrupt reporting for the channel conversion sets.
EXAMPLE
if(HW_LRADC_CTRL1.TOUCH_DETECT_IRQ == BV_LRADC_CTRL1_TOUCH_DETECT_IRQ__PENDING){
}
Address:
2274
Reset
// Then handle the interrupt.
HW_LRADC_CTRL1.TOUCH_DETECT_IRQ_EN = BV_LRADC_CTRL1_TOUCH_DETECT_IRQ_EN__DISABLE;
SCHEDULE
Bit
W
RSRVD1
R
Field
15 8
7 0
31
0
RSRVD2
HW_LRADC_CTRL1
30
0
Reserved
Setting a bit to one schedules the corresponding LRADC channel to be converted. When the conversion of
a scheduled channel is completed the corresponding schedule bit is reset by the hardware and the
corresponding interrupt request is set to one. Thus any thread can request a conversion asynchronously
from any other thread.
29
0
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
HW_LRADC_CTRL0 field descriptions (continued)
28
0
8005_0000h base + 10h offset = 8005_0010h
27
0
26
0
25
0
24
0
Description
23
0
22
0
21
0
20
0
Freescale Semiconductor, Inc.
19
0
18
0
17
0
16
0