MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 2187
MCIMX286CVM4B
Manufacturer Part Number
MCIMX286CVM4B
Description
IC MPU I.MX286 289MAPBGA
Manufacturer
Freescale Semiconductor
Series
i.MX28r
Datasheets
1.MCIMX283DVM4B.pdf
(70 pages)
2.MCIMX283DVM4B.pdf
(2 pages)
3.MCIMX283DVM4B.pdf
(2327 pages)
4.MCIMX283DVM4B.pdf
(20 pages)
Specifications of MCIMX286CVM4B
Core Processor
ARM9
Core Size
32-Bit
Speed
454MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
Peripherals
DMA, I²S, LCD, POR, PWM, WDT
Program Memory Size
128KB (32K x 32)
Program Memory Type
Mask ROM
Ram Size
32K x 32
Voltage - Supply (vcc/vdd)
1.25 V ~ 5.25 V
Data Converters
A/D 17x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
289-LFBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of I /o
-
Eeprom Size
-
Lead Free Status / Rohs Status
Compliant
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HW_PXP_OLnSIZE_WR(4,0x10000401); // 32x8 overlay at offset +128+0
Address:
Re-
34.4.43 PXP Overlay 4 Parameters (HW_PXP_OL4PARAM)
This register contains buffer parameters for the Overlay 4 input buffer.
The S1 Overlay 4 Parameter register provides additional controls for Overlay 4.
EXAMPLE
u32 olparam;
HW_PXP_OLnPARAM_WR(4,olparam);
Address:
Freescale Semiconductor, Inc.
set
Reset
Bit
W
R
Bit
31
W
0
HEIGHT
R
XBASE
YBASE
WIDTH
31 24
23 16
Field
15 8
7 0
olparam
olparam |= BF_PXP_OLnPARAM_ALPHA_CNTL(BV_PXP_OLnPARAM_ALPHA_CNTL__ROPs);
olparam |= BF_PXP_OLnPARAM_FORMAT
olparam |= BF_PXP_OLnPARAM_ROP
30
0
31
0
29
0
HW_PXP_OL4PARAM
HW_PXP_OL4SIZE
XBASE
28
0
30
0
This field indicates the X-coordinate (in blocks) of the top-left NxN block in the overlay within the output
frame buffer.
This field indicates the Y-coordinate (in blocks) of the top-left NxN block in the overlay within the output
frame buffer.
Indicates number of horizontal NxN blocks in the image (non-rotated).
Indicates the number of vertical NxN blocks in the image (non-rotated).
27
= BF_PXP_OLnPARAM_ENABLE
0
26
0
29
0
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
25
0
24
0
28
0
23
0
HW_PXP_OL4SIZE field descriptions
8002_A000h base + 310h offset = 8002_A310h
22
0
27
8002_A000h base + 320h offset = 8002_A320h
0
21
// enable overlay to perform XOR ROP using RGB8888 overlay
0
YBASE
20
0
26
0
RSVD1
19
0
18
25
0
0
(1);
(BV_PXP_OLnPARAM_FORMAT__ARGB8888);
(BV_PXP_OLnPARAM_ROP__XOROL);
17
0
16
24
0
0
15
0
Description
23
14
0
0
13
0
WIDTH
22
12
0
0
11
0
21
0
10
0
0
9
20
0
Chapter 34 Pixel Pipeline (PXP)
0
8
0
7
19
0
0
6
0
5
HEIGHT
18
0
0
4
ROP
3
0
17
0
0
2
0
1
2187
16
0
0
0
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