MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 2092

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

Programmable Registers
When the LCDIF is behaving as a master, this address points to the address of the next
frame of data that will be sent out through the LCDIF. It is upto the software to make sure
that this register is programmed before the end of the current frame, otherwise it might
result in old data going out the LCDIF. This address must always be double-word aligned.
Address:
Re-
33.4.7 LCD Interface Timing Register (HW_LCDIF_TIMING)
The LCD interface timing register controls the various setup and hold times enforced by
the LCD interface in the 6800/8080 system and VSYNC modes of operation.
The values used in this register are dependent on the particular LCD controller used, consult
the users manual for the particular controller for required timings. Each field of the register
must be non-zero, therefore the minimum value is: 0x01010101. NOTE: the timings are
not automatically adjusted if the CLK_DIS_LCDIFn frequency changes--it may be necessary
to adjust the timings if CLK_DIS_LCDIFn changes. NOTE: Each field in this register must
be non-zero for the system and VSYNC modes to function. The settings in this register do
not affect the DOTCLK and DVI modes.
Address:
Re-
2092
set
set
Bit
Bit
W
W
R
R
CMD_HOLD
31
31
0
0
ADDR
31 24
Field
31 0
Field
30
30
0
0
29
29
0
CMD_HOLD
0
HW_LCDIF_NEXT_BUF
HW_LCDIF_TIMING
28
28
0
0
start address of next buffer
Number of CLK_DIS_LCDIFn cycles that the DCn signal is active after CEn is deasserted.
27
27
0
0
26
26
0
0
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
25
25
0
0
24
24
0
0
HW_LCDIF_NEXT_BUF field descriptions
23
23
0
0
HW_LCDIF_TIMING field descriptions
8003_0000h base + 60h offset = 8003_0060h
22
22
0
0
8003_0000h base + 50h offset = 8003_0050h
CMD_SETUP
21
21
0
0
20
20
0
0
19
19
0
0
18
18
0
0
17
17
0
0
ADDR
16
16
0
0
15
15
0
0
Description
Description
14
14
0
0
13
13
0
DATA_HOLD
0
12
12
0
0
11
11
0
0
10
10
0
0
0
0
9
9
0
0
8
8
Freescale Semiconductor, Inc.
0
0
7
7
0
0
6
6
DATA_SETUP
0
0
5
5
0
0
4
4
3
0
3
0
0
0
2
2
0
0
1
1
0
0
0
0