MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 468

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

Programmable Registers
468
Reset
HALTONTERMINATE
NANDWAIT4READY
WAIT4ENDCMD
Bit
W
XFER_COUNT
R
IRQONCMPLT
SEMAPHORE
CMDWORDS
NANDLOCK
RSVD1
CHAIN
31 16
15 12
15
11 9
Field
0
8
7
6
5
4
3
2
CMDWORDS
14
0
13
0
This field indicates the number of bytes to transfer to or from the appropriate PIO register in the
HSADC device HW_HSADC_FIFO_DATA register. A value of 0 indicates a 64 Kbytes transfer.
This field indicates the number of command words to send to the HSADC, starting with the base PIO
address of the HSADC (HW_HSADC_CTRL0) and increment from there. Zero means transfer NO
command words
Reserved, always set to zero.
A value of one indicates that the channel immediately terminates the current descriptor and halts the
DMA channel if a terminate signal is set. A value of 0 still causes an immediate terminate of the
channel if the terminate signal is set, but the channel continues as if the count had been exhausted,
meaning it honors IRQONCMPLT, CHAIN, SEMAPHORE, and WAIT4ENDCMD.
A value of one indicates that the channel waits for the end of command signal to be sent from the
APBH device to the DMA before starting the next DMA command.
A value of one indicates that the channel decrements its semaphore at the completion of the current
command structure. If the semaphore decrements to zero, then this channel stalls until software
increments it again.
A value of one indicates that the NAND DMA channel waits until the NAND device reports \'ready\'
before executing the command. It is ignored for non-NAND DMA channels.
A value of one indicates that the NAND DMA channel remains locked in the arbiter at the expense of
other NAND DMA channels. It is ignored for non-NAND DMA channels..
A value of one indicates that the channel will cause the interrupt status bit to be set upon completion
of the current command, i.e. after the DMA transfer is complete.
A value of one indicates that another command is chained onto the end of the current command
structure. At the completion of the current command, this channel will follow the pointer in
HW_APBH_CH12_CMDAR to find the next command.
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
12
0
HW_APBH_CH12_CMD field descriptions
11
0
RSVD1
10
0
0
9
0
8
Description
0
7
0
6
5
0
4
0
Freescale Semiconductor, Inc.
0
3
0
2
COMMAND
0
1
0
0