MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 1147

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

14.8.42 DRAM Control Register 44 (HW_DRAM_CTL44)
This is a DRAM configuration register.
Address:
Re-
Freescale Semiconductor, Inc.
set
Bit
W
R
TWR_INT
31
0
RSVD1
RSVD4
RSVD3
RSVD2
RSVD1
15 14
31 28
27 24
TWTR
23 21
20 16
15 11
TRRD
TREF
TRTP
Field
13 0
Field
10 8
7 3
2 0
RSVD4
30
0
29
0
HW_DRAM_CTL44
28
0
Always write zeroes to this field.
DRAM TREF parameter in cycles.
Defines the DRAM cycles between refresh commands.
Always write zeroes to this field.
DRAM TWTR parameter in cycles.
Sets the number of cycles needed to switch from a write to a read operation, as dictated by the DDR SDRAM
specification.
Always write zeroes to this field.
DRAM TWR parameter in cycles.
Defines the DRAM write recovery time, in cycles.
Always write zeroes to this field.
DRAM TRTP parameter in cycles.
For DDR1, this parameter has no meaning. For LPDDR1 or DDR2, defines the DRAM tRTP (read to
pre-charge time) parameter, in cycles.
Always write zeroes to this field.
DRAM TRRD parameter in cycles.
Defines the DRAM activate to activate delay for different banks, in cycles.
27
0
TWTR
26
0
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
25
0
HW_DRAM_CTL43 field descriptions (continued)
24
0
23
0
RSVD3
HW_DRAM_CTL44 field descriptions
800E_0000h base + B0h offset = 800E_00B0h
22
0
21
0
20
0
TWR_INT
19
0
18
0
17
0
16
0
15
0
Description
Description
14
0
RSVD2
13
0
12
0
Chapter 14 External Memory Interface (EMI)
11
0
10
0
TRTP
0
9
0
8
0
7
0
6
RSVD1
0
5
0
4
3
0
0
2
TRRD
0
1
1147
0
0