MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 973

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

SSP2 and SSP3 are used for SPI boot mode.
12.10.1 SSP Pin Configuration
SSP boot mode supports the standard package and the small package of i.MX28.
12.10.2 Media Format
The media is arbitrarily partitioned into 128-byte sectors. An optional configuration block
may reside on the media at byte address 0. This block has the following format:
//! \brief Spi media configuration block structs
typedef struct _spi_ConfigBlockFlags
{
} spi_ConfigBlockFlags_t;
typedef struct _spi_ConfigBlockClocks
{
} spi_ConfigBlockClocks_t;
typedef struct _spi_ConfigBlock // Little Endian
{
Freescale Semiconductor, Inc.
SCK
DETECT
CMD
DATA7
DATA6
DATA5
DATA4
DATA3
DATA2
DATA1
DATA0
Pins
SSP
uint32_t
uint32_t
ssp_ClockConfig_t
SSP0_CLK
SSP0_DETECT
SSP0_CMD
SSP0_DATA7
SSP0_DATA6
SSP0_DATA5
SSP0_DATA4
SSP0_DATA3
SSP0_DATA2
SSP0_DATA1
SSP0_DATA0
SSP0
DisableFastRead:1; // Ignored for Spis
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
GPMI_WRN
GPMI_RDY0
GPMI_RDY1
GPMI_D07
GPMI_D06
GPMI_D05
GPMI_D04
GPMI_D03
GPMI_D02
GPMI_D01
GPMI_D00
Table 12-26. SSP Ports Pin-Mux Configuration
SizeOfSspClockConfig; // sizeof(ssp_ClockConfig_t)
SspClockConfig;
SSP1
SSP2_SCK
—
SSP2_MOSI
—
—
—
—
SSP2_S30
—
—
SSP2_MISO
// 0 - Do not disable fast reads
// 1 - Disable fast reads
SSP2
SSP3_SCK
—
SSP3_MOSI
—
—
—
—
SSP3_S30
—
—
SSP3_MISO
(standard package)
// SSP clock configuration structure. A null
//
SSP3
structure indicates no clock change.
GPMI_RDN
—
GPMI_RESETN
—
—
—
—
GPMI_CE1N
—
—
GPMI_CE0N
(small package)
SSP3
Chapter 12 Boot Modes
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