MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 1346

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

Programmable Registers
17.10.17 SSP Status Register (HW_SSP_STATUS)
SSP Read Only Status Registers.
Various SSP status fields are provided in this register.
Address:
1346
Reset
Reset
SLV_FORCE_
SLV_DLY_
Bit
Bit
W
W
TARGET
ENABLE
R
R
RESET
Field
UPD
6 3
2
1
0
31
15
1
0
HW_SSP_STATUS
30
14
1
0
The delay target for the SSP read clock is can be programmed in 1/16th increments of an SSPCLK half-period.
So the input read-clock can be delayed relative input data from (SSPCLK/2)/16 to SSPCLK/2.
Setting this bit to 1, forces the slave delay line to update to the DLL calibrated value immediately. The slave
delay line shall update automatically based on the SLV_UPDATE_INT interval or when a DLL lock condition
is sensed. Subsequent forcing of the slave-line update can only occur if SLV_FORCE_UP is set back to 0
and then asserted again (edge triggered).
Setting this bit to 1 force a reset on DLL. This will cause the DLL to lose lock and re-calibrate to detect an
SSPCLK half period phase shift. This signal is used by the DLL as edge-sensitive, so in order to create a
subsequent reset, RESET must be taken low and then asserted again.
Set this bit to 1 to enable the DLL and delay chain; otherwise; set to 0 to bypasses DLL. Note that using the
slave delay line override feature with SLV_OVERRIDE and SLV_OVERRIDE VAL, the DLL does not need
to be enabled.
29
13
1
0
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
HW_SSP_DLL_CTRL field descriptions (continued)
28
12
0
0
8001_0000h base + 100h offset = 8001_0100h
27
11
0
0
26
10
0
0
RSVD3
25
0
0
9
24
0
0
8
Description
23
0
0
7
RSVD1
22
0
0
6
21
0
5
1
20
0
4
0
Freescale Semiconductor, Inc.
19
0
0
3
18
0
0
2
17
0
0
1
BUSY
16
0
0
0