MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 1836

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

Reset and Stop Functions
29.6.3 Port 0 Input Protection
The port 0 input buffer is protected for application errors that abort a frame without writing
a proper eop to the interface. The next frame then written to the port 0 transmit interface
will be concatenated with whatever data was already written before, but the frame will be
marked with an error and hence will be forwarded and transmitted with an error indication
(mii tx error).
If the port0 input buffer is reset (by deasserting PORT_ENA receive enable bit) while a
frame is transferred to the switch internally, the frame transfer will be aborted in a clean
way (producing an eop with error indication) to avoid blocking the switch.
29.6.4 Port 1,2 Input Protection
Ports 1 and 2 are protected for a second SOP in case the MAC is reset in the middle of a
receive transaction to the switch hence did not produce a proper EOP to the switch. The
next frame will be concatenated with whatever was provided to the switch before and marked
with an error.
If the MAC is stopped in the middle of a transaction, the switch is blocked, waiting for the
EOP, not serving any of the other ports. Clearing the PORT_ENA receive enable bit in this
situation will terminate the frame with an error internally to the switch hence remove the
blocking condition.
29.6.5 DMA Bus Error
When the DMA bus error input (dma_eberr_int) is asserted, the DMA registers are all
cleared. If the corresponding interrupt was enabled the ipi_eberr_int pin will be asserted.
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• If any port's transmit enable bit is cleared, the shared memory will continue delivering
• If any port's receive enable bit is cleared while a frame is transferred, this frame will
the frames stored currently for a port as normal (that is, flushing the memory). New
frames will be discarded before they are written into the shared memory. That is, no
invalid frame will appear on the MAC interfaces after disabling or re-enabling a port.
be aborted with an error internally. The port's ready indication will stay asserted (output
ff_tx_rdy=1) to flush any application data. Reenabling the port at any time will ignore
any input data until a sop starts a new frame.
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
Freescale Semiconductor, Inc.