MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 1349

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MCIMX286CVM4B

Manufacturer Part Number
MCIMX286CVM4B
Description
IC MPU I.MX286 289MAPBGA
Manufacturer
Freescale Semiconductor
Series
i.MX28r

Specifications of MCIMX286CVM4B

Core Processor
ARM9
Core Size
32-Bit
Speed
454MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
Peripherals
DMA, I²S, LCD, POR, PWM, WDT
Program Memory Size
128KB (32K x 32)
Program Memory Type
Mask ROM
Ram Size
32K x 32
Voltage - Supply (vcc/vdd)
1.25 V ~ 5.25 V
Data Converters
A/D 17x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
289-LFBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of I /o
-
Eeprom Size
-
Lead Free Status / Rohs Status
Compliant
17.10.19 SSP Debug Register (HW_SSP_DEBUG)
SSP Read Only Debug Registers.
Debug Register provide access to State machines.
Address:
Freescale Semiconductor, Inc.
Reset
Reset
DATACRC_ERR
DATA_STALL
REF_LOCK
SLV_LOCK
REF_SEL
Bit
Bit
SLV_SEL
W
W
DAT_SM
R
R
31 28
26 24
Field
13 8
Field
7 2
27
1
0
31
15
0
0
DATACRC_ERR
HW_SSP_DEBUG
MMC_SM
30
14
0
0
Reference delay line select status.
Slave delay line select status
Reference DLL lock status. This signifies that the DLL has detected and locked to a half-phase SSPCLK
shift, allowing the slave delay-line to perform programmed clock delays.
Slave delay-line lock status. This signifies that a valid calibration has been set to the slave-delay line and
that the slave-delay line is implementing the programmed delay value.
Data CRC error
MMC mode: FIFO transfer not ready
MMC dataxfer state machine
0x0
0x2
0x3
0x4
0x5
29
13
0
0
DSM_IDLE —
DSM_WORD —
DSM_CRC1 —
DSM_CRC2 —
DSM_END —
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
HW_SSP_DLL_STS field descriptions (continued)
28
12
0
0
8001_0000h base + 120h offset = 8001_0120h
HW_SSP_DEBUG field descriptions
DATA_
STALL
CMD_SM
27
11
0
0
26
10
0
0
DAT_SM
SSP_
CMD
25
0
0
9
RESP
SSP_
24
0
0
8
Description
Description
23
0
0
7
22
0
0
6
RSVD1
Chapter 17 Synchronous Serial Ports (SSP)
21
0
5
0
SSP_RXD
20
0
4
0
CMD_
OE
19
0
0
3
18
0
0
2
DMA_SM
17
0
0
1
1349
16
0
0
0

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