MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 1007

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

Each channel can be programmed as being in either the high-priority or low-priority
arbitration pool, depending on the setting in the HIGH_PRIORITY_CHANNEL field of
the HW_DCP_CHANNELCTRL register. When the corresponding bit is programmed as
a 1, the channel arbitrates in the high-priority pool; otherwise, it arbitrates in the low-priority
pool. Once a channel has been selected, it completes one packet and then the arbiter
re-arbitrates. The channel that just completed participates in the new arbitration round.
13.2.5.2 Channel Recovery Timers
Each channel also contains a channel recovery timer in its HW_DCP_CHnOPTS register.
The purpose of the recovery timer is to keep the channel inactive for a period of time after
it completes an operation. This capability could be used for a high-priority channel to ensure
that at least some lower-priority requests get serviced between packets or to simply allow
more timeslices for other channels to perform operations. The value programmed into the
recovery timers register delays the channel from operations until 16 times the programmed
value. Any non-zero value should prevent the channel from participating in the next
arbitration cycle.
13.2.6 Programming Channel Operations
The control logic block maintains the channel pointers and manages arbitration and context
switching between the different channels. It also manages the fetching of work packets and
data fetch/store operations from the AXI master interface and coordinates the actions of the
hashing and encryption blocks.
The control logic maintains four channels that allow software to effectively create four
independent work sets for the DCP module. Software can construct chained control packets
in memory that describe encryption/hashing/memcopy operations to the hardware unit. The
address for this first control packet can be written to one of the four virtual channels and
Freescale Semiconductor, Inc.
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
Figure 13-9. DCP Arbitration
High
Low
0
1
0
Channels
1
1
0
2
1
0
3
1
0
Chapter 13 Data Co-Processor (DCP)
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