MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 1177

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

14.8.79 DRAM Control Register 84 (HW_DRAM_CTL84)
This is a DRAM configuration register.
Address:
Re-
Freescale Semiconductor, Inc.
set
Bit
ODT_WR_MAP_
W
R
31
0
RSVD4
RSVD3
31 28
27 24
23 20
Field
Field
CS3
RSVD4
30
0
29
0
HW_DRAM_CTL84
28
0
Example: If the system consists of 4 chip selects and odt_rd_map_cs0 is set to 'b0010, then when CS0 is
performing a read, CS1 will have active ODT termination. And if odt_rd_map_cs0 was set to 'b1000, then
instead CS3 would be active.
Bit [3] = CS3 will have active ODT termination when chip select X is performing a read.
Bit [2] = CS2 will have active ODT termination when chip select X is performing a read.
Bit [1] = CS1 will have active ODT termination when chip select X is performing a read.
Bit [0] = CS0 will have active ODT termination when chip select X is performing a read.
Etc.
Always write zeroes to this field.
Determines which chip(s) will have termination when a write occurs on chip 3.
Sets up which (if any) chip(s) will have their ODT termination active while a write occurs on chip select X.
EMI will define this parameter at default for internal testing. The user is required is to change this setting to
meet system specifications.
Example: If the system consists of 4 chip selects and odt_wr_map_cs0 is set to 'b0010, then when CS0 is
performing a write, CS1 will have active ODT termination. And if odt_wr_map_cs0 was set to 'b1000, then
instead CS3 would be active.
Bit [3] = CS3 will have active ODT termination when chip select X is performing a write.
Bit [2] = CS2 will have active ODT termination when chip select X is performing a write.
Bit [1] = CS1 will have active ODT termination when chip select X is performing a write.
Bit [0] = CS0 will have active ODT termination when chip select X is performing a write.
Etc.
Always write zeroes to this field.
27
0
ODT_WR_
MAP_CS3
26
0
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
25
0
HW_DRAM_CTL83 field descriptions (continued)
24
0
23
0
HW_DRAM_CTL84 field descriptions
800E_0000h base + 150h offset = 800E_0150h
RSVD3
22
0
21
0
20
0
19
0
ODT_WR_
MAP_CS2
18
0
17
0
16
0
15
0
Description
Description
RSVD2
14
0
13
0
12
0
Chapter 14 External Memory Interface (EMI)
11
0
ODT_WR_
MAP_CS1
10
0
0
9
0
8
0
7
RSVD1
0
6
0
5
0
4
3
0
ODT_WR_
MAP_CS0
0
2
0
1
1177
0
0