MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 1985

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

Freescale Semiconductor, Inc.
RSVD2
RSVD1
ULPII
NAKI
Field
HCH
RCL
SLI
AS
PS
16
15
14
13
12
11
10
9
8
NAK Interrupt Bit.
It is set by hardware when for a particular endpoint both the TX/RX Endpoint NAK bit and the corresponding
TX/RX Endpoint NAK Enable bit are set. This bit is automatically cleared by hardware when the all the
enabled TX/RX Endpoint NAK bits are cleared.
Asynchronous Schedule Status.
This bit reports the current real status of the Asynchronous Schedule. When set to 0 the asynchronous
schedule status is disabled and if set to 1 the status is enabled. The Host Controller is not required to
immediately disable or enable the Asynchronous Schedule when software transitions the Asynchronous
Schedule Enable bit in the USBCMD register. When this bit and the Asynchronous Schedule Enable bit are
the same value, the Asynchronous Schedule is either enabled (1) or disabled (0).
Only used by the host controller.
Periodic Schedule Status.
0 = Default.
This bit reports the current real status of the Periodic Schedule. When set to 0 the periodic schedule is
disabled, and if set to 1 the status is enabled. The Host Controller is not required to immediately disable or
enable the Periodic Schedule when software transitions the Periodic Schedule Enable bit in the USBCMD
register. When this bit and the Periodic Schedule Enable bit are the same value, the Periodic Schedule is
either enabled (1) or disabled (0).
Only used by the host controller.
Reclamation.
0 = Default.
This is a read-only status bit used to detect an empty asynchronous schedule.
Only used by the host controller; 0 in device mode.
HC Halted.
1 = Default.
This bit is a 0 whenever the Run/Stop bit is a 1. The Host Controller sets this bit to 1 after it has stopped
executing because of the Run/Stop bit being set to 0, either by software or by the Host Controller hardware
(e.g. internal error).
Only used by the host controller; 0 in device mode.
Reserved.
Not present in this implementation.
Reserved.
DC Suspend.
0 = Default.
When a device controller enters a suspend state from an active state, this bit will be set to a 1. The device
controller clears the bit upon exiting from a suspend state.
Only used by the device controller.
HW_USBCTRL_USBSTS field descriptions (continued)
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
Chapter 31 USB High-Speed On-the-Go Host Device Controller
Description
1985