MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 1243

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

The GPMI programming for this DELAY depends on the GPMICLK period. The GPMI
DLL will not function properly if the GPMICLK period is greater than 32 ns: disable the
DLL if this is the case. If the GPMICLK period is greater than 16 ns (and not greater than
32 ns), set the HW_GPMI_CTRL1_HALF_PERIOD=1; This will cause the DLL reference
period (RP) to be one-half of the GPMICLK period. If the GPMICLK period is 16 ns or
less then set the HW_GPMI_CTRL1_HALF_PERIOD=0; This will cause the DLL reference
period (RP) to be equal to the GPMICLK period. DELAY is a multiple (0 to 1.875) of RP.
The HW_GPMI_CTRL1_RDN_DELAY is encoded as a 1-bit integer and 3-bit fraction
delay factor. See table below. DELAY is a multiple of the delay factor and the reference
period:
DELAY = DelayFactor x RP or DELAY = HW_GPMI_CTRL1_RDN_DELAY x 0.125 x
RP.
Use this equation to calculate the value for HW_GPMI_CTRL1_RDN_DELAY. Then set
HW_GPMI_CTRL1_DLL_ENABLE=1.
Freescale Semiconductor, Inc.
HW_GPMI_CTRL1_RDN_DELAY
Delay Factor
HW_GPMI_CTRL1_RDN_DELAY
Delay Factor
When (tREA + 4ns) is greater than or equal to tRP, a delay of the FeedbackRDN is required to sample to nand read data
Read Data
RDN
FeedbackRDN
Read Data
RDN
FeedbackRDN
(tREA + 4ns) is less than tRP, no delay is required on rising edge of FeedbackRDN to sample Read Data
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
GPMI NAND Read Path Timing Diagram (Non-EDO)
GPMI NAND Read Path Timing Diagram (EDO mode)
Figure 15-3. NAND Read Path Timing
tRP
tREA
tREA
0
0.000
8
1.000
tRP
A
A
1
0.125
9
1.125
2
0.250
10
1.250
Chapter 15 General-Purpose Media Interface(GPMI)
Delay
B
B
3
0.375
11
1.375
4
0.500
12
1.500
5
0.625
13
1.625
C
C
6
0.750
14
1.750
7
0.875
15
1.875
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