MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 1325

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

17.8.2.1 SD/MMC Multiple Block Transfers
The SSP supports SD/MMC multiple block transfers. The CPU or DMA will configure the
SD/MMC controller to issue a Multi-Block Read or Write command. If DMA is used, then
the first descriptor issues the multi-block read/write command and receives/sends the first
block (512 bytes) of data. Subsequent DMA descriptors only receive/send blocks of data
and do not issue new SD/MMC commands. If the card is configured for an open-ended
multi-block transfer, then the last DMA descriptor needs to issue a STOP command to the
card. Multiple blocks can also be transferred with a single DMA descriptor.
After each block of data has been transferred, the SSP sends/receives the CRC and checks
the CRC or the CRC token. If the CRC is correct, then the SSP signals the DMA that it is
completed.
The SSP supports transferring multiple SD/MMC blocks per DMA descriptor. The SSP
state machine needs to know the number of blocks and the size of a block. When
HW_SSP_BLOCK_SIZE_BLOCK_COUNT is non-zero, the actual block size is:
For example, setting a value of 9 will result in a block size of 512 bytes. When
BLOCK_COUNT is 0, BLOCK_SIZE is ignored and the bit field
HW_SSP_XFER_SIZE_XFER_COUNT represents the single block size or the number of
byte to transfer. This must satisfy the equation:
for BLOCK_COUNT greater than 0.
17.8.2.2 eMMC DDR operation
When performing a single block or multiple block transfer, the SSP has an option of using
DDR operation by setting DBL_DATA_RATE_EN bit in HW_SSP_CMD0 register. When
performing a DDR operation, the timing relationship between SCK and DATA can be
programmed to suit different needs. The highly recommended settings are in the following
(but not necessary):
Freescale Semiconductor, Inc.
0x1 shiftleft BLOCK_SIZE
HW_SSP_XFER_SIZE_XFER_COUNT = (0x1 shiftleft BLOCK_SIZE) x
(BLOCK_COUNT+1)
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
Chapter 17 Synchronous Serial Ports (SSP)
1325