MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 1664

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

Programmable Registers
Address:
Re-
26.4.4 ENET MAC Transmit Descriptor Active Register
The Transmit Descriptor Active Register (TDAR) is a command register which the user
writes to indicate the transmit descriptor ring has been updated (transmit buffers have been
produced by the driver with the ready bit set in the buffer descriptor)
When the register is written, the TDAR bit is set. This value is independent of the data
actually written by the user. When set, the uDMA polls the transmit descriptor ring and
processes transmit frames (provided ether_en is also set). Once the uDMA polls a transmit
descriptor that has a ready bit not set, the uDMA clears the TDAR bit and ceases transmit
descriptor ring polling until the user sets the bit again to signify additional descriptors have
been placed into the transmit descriptor ring. The TDAR register is cleared at reset, when
ether_en transitions from asserted to de-asserted, or when the ecr_reset is set.
Address:
Re-
1664
set
set
Bit
Bit
W
W
R
R
31
31
RSRVD0
RSRVD1
0
0
31 25
RDAR
Field
23 0
24
30
30
0
0
29
29
RSRVD0
RSRVD0
0
0
(HW_ENET_MAC_TDAR)
HW_ENET_MAC_RDAR
HW_ENET_MAC_TDAR
28
28
0
0
Reserved bits. Write as 0.
Set to 1 when this register is written, regardless of the value written. Cleared by the uDMA when no additional
empty descriptors remain in the receive ring. Also cleared when ether_en transitions from asserted to
de-asserted.
Reserved bits. Write as 0.
27
27
0
0
26
26
0
0
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
25
25
0
0
24
24
0
0
HW_ENET_MAC_RDAR field descriptions
23
23
0
0
22
22
0
0
800F_0000h base + 14h offset = 800F_0014h
800F_0000h base + 10h offset = 800F_0010h
21
21
0
0
20
20
0
0
19
19
0
0
18
18
0
0
17
17
0
0
16
16
0
0
15
15
0
0
Description
14
14
0
0
13
13
0
0
RSRVD1
RSRVD1
12
12
0
0
11
11
0
0
10
10
0
0
0
0
9
9
0
0
8
8
Freescale Semiconductor, Inc.
0
0
7
7
0
0
6
6
0
0
5
5
0
0
4
4
3
0
3
0
0
0
2
2
0
0
1
1
0
0
0
0