MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 1443

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MCIMX286CVM4B

Manufacturer Part Number
MCIMX286CVM4B
Description
IC MPU I.MX286 289MAPBGA
Manufacturer
Freescale Semiconductor
Series
i.MX28r

Specifications of MCIMX286CVM4B

Core Processor
ARM9
Core Size
32-Bit
Speed
454MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
Peripherals
DMA, I²S, LCD, POR, PWM, WDT
Program Memory Size
128KB (32K x 32)
Program Memory Type
Mask ROM
Ram Size
32K x 32
Voltage - Supply (vcc/vdd)
1.25 V ~ 5.25 V
Data Converters
A/D 17x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
289-LFBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of I /o
-
Eeprom Size
-
Lead Free Status / Rohs Status
Compliant
20.4.20 Value of OTP Bank2 Word1 (Freescale OPS0)
OTP banks must be open through HW_OCOTP_CTRL[RD_BANK_OPEN] before reading
this register. Reading this register without having HW_OCOTP_CTRL[RD_BANK_OPEN]
set and HW_OCOTP_CTRL[BUSY] clear, will result in HW_OCOTP_CTRL[ERROR]
being set and 0xBADA_BADA being returned.
Shadowed memory mapped access to OTP Bank 2, word 1 (ADDR = 0x11).
Address:
Re-
Freescale Semiconductor, Inc.
set
Bit
W
R
CRYPTODCP
CRYPTOKEY
SHADOW
31
0
HWSW_
CUST3
CUST2
CUST1
CUST0
Field
Field
31 0
BITS
30
6
5
4
3
2
1
0
0
29
0
HW_OCOTP_OPS0
(HW_OCOTP_OPS0)
28
0
Status of HW/SW Capability shadow register lock. When set, over-ride of HW/SW capabality shadow bits
is blocked.
Status of read lock bit for DCP APB crypto access. When set, the DCP will disallow reads of its crypto keys
through its APB interface.
Status of crypto key region (ADDR = 0x04-0x07) read/write lock bit. When set, region is locked.
Status of customer region word (ADDR = 0x03) write lock bit. When set, the region is locked.
Status of customer region word (ADDR = 0x02) write lock bit. When set, the region is locked.
Status of customer region word (ADDR = 0x01) write lock bit. When set, the region is locked.
Status of customer region word (ADDR = 0x00) write lock bit. When set, the region is locked.
Reflects value of OTP Bank 2, word 1 (ADDR = 0x11)
27
0
26
0
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
25
HW_OCOTP_LOCK field descriptions (continued)
0
24
0
23
0
HW_OCOTP_OPS0 field descriptions
8002_C000h base + 130h offset = 8002_C130h
22
0
21
0
20
0
19
0
18
0
17
0
16
0
BITS
15
0
Description
Description
14
0
13
0
12
0
Chapter 20 On-Chip OTP (OCOTP) Controller
11
0
10
0
0
9
0
8
0
7
0
6
0
5
0
4
3
0
0
2
0
1
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