MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 1359

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

Freescale Semiconductor, Inc.
8001_C0A0
8001_C0C0
8001_C0D0
8001_C0E0
8001_C1A0
8001_C1B0
8001_C1C0
8001_C1D0
8001_C1E0
8001_C2A0
8001_C2B0
8001_C060
8001_C070
8001_C080
8001_C090
8001_C100
8001_C110
8001_C120
8001_C130
8001_C140
8001_C150
8001_C160
8001_C170
8001_C180
8001_C190
8001_C280
8001_C290
Absolute
address
(hex)
Software Write-Once Register (HW_DIGCTL_WRITEONCE)
BIST Control Register (HW_DIGCTL_BIST_CTL)
DIGCTL Status Register (HW_DIGCTL_BIST_STATUS)
Entropy Register (HW_DIGCTL_ENTROPY)
Entropy Latched Register
(HW_DIGCTL_ENTROPY_LATCHED)
Digital Control Microseconds Counter Register
(HW_DIGCTL_MICROSECONDS)
Digital Control Debug Read Test Register
(HW_DIGCTL_DBGRD)
Digital Control Debug Register (HW_DIGCTL_DBG)
USB LOOP BACK (HW_DIGCTL_USB_LOOPBACK)
SRAM Status Register 0 (HW_DIGCTL_OCRAM_STATUS0)
SRAM Status Register 1 (HW_DIGCTL_OCRAM_STATUS1)
SRAM Status Register 2 (HW_DIGCTL_OCRAM_STATUS2)
SRAM Status Register 3 (HW_DIGCTL_OCRAM_STATUS3)
SRAM Status Register 4 (HW_DIGCTL_OCRAM_STATUS4)
SRAM Status Register 5 (HW_DIGCTL_OCRAM_STATUS5)
SRAM Status Register 6 (HW_DIGCTL_OCRAM_STATUS6)
SRAM Status Register 7 (HW_DIGCTL_OCRAM_STATUS7)
SRAM Status Register 8 (HW_DIGCTL_OCRAM_STATUS8)
SRAM Status Register 9 (HW_DIGCTL_OCRAM_STATUS9)
SRAM Status Register 10
(HW_DIGCTL_OCRAM_STATUS10)
SRAM Status Register 11
(HW_DIGCTL_OCRAM_STATUS11)
SRAM Status Register 12
(HW_DIGCTL_OCRAM_STATUS12)
SRAM Status Register 13
(HW_DIGCTL_OCRAM_STATUS13)
Digital Control Scratch Register 0 (HW_DIGCTL_SCRATCH0)
Digital Control Scratch Register 1 (HW_DIGCTL_SCRATCH1)
Digital Control ARM Cache Register
(HW_DIGCTL_ARMCACHE)
Debug Trap Control and Status for AHB Layer 0 and 3
(HW_DIGCTL_DEBUG_TRAP)
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
HW_DIGCTL memory map (continued)
Register name
Chapter 19 Digital Control (DIGCTL) and On-Chip RAM
(in bits)
Width
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
A5A5_A5A5h
789A_BCDEh
Reset value
4000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
8765_4321h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
19.4.10/1375
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19.4.16/1380
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19.4.33/1393
19.4.7/1369
19.4.8/1370
19.4.9/1372
Section/
page
1359