MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 1986

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

Programmable Registers
1986
Field
URI
SRI
AAI
SEI
FRI
PCI
7
6
5
4
3
2
SOF Received.
0 = Default.
When the device controller detects a Start Of (micro) Frame, this bit will be set to a 1. When a SOF is
extremely late, the device controller will automatically set this bit to indicate that an SOF was expected.
Therefore, this bit will be set roughly every 1ms in device FS mode and every 125ms in HS mode and will
be synchronized to the actual SOF that is received. Since the device controller is initialized to FS before
connect, this bit will be set at an interval of 1ms during the prelude to connect and chirp.
In host mode, this bit will be set every 125us and can be used by host controller driver as a time base.
Software writes a 1 to this bit to clear it.
This is a non-EHCI status bit.
USB Reset Received.
0 = Default.
When the device controller detects a USB Reset and enters the default state, this bit will be set to a 1.
Software can write a 1 to this bit to clear the USB Reset Received status bit.
Only used by the device controller.
NOTE: This bit should not normally be used to detect reset during suspend, as this block will normally be
clock-gated during that time. Use HW_USBPHY_CTRL_RESUME_IRQ, instead.
Interrupt on Async Advance.
0 = Default.
System software can force the host controller to issue an interrupt the next time the host controller advances
the asynchronous schedule by writing a 1 to the Interrupt on Async Advance Doorbell bit in the USBCMD
register. This status bit indicates the assertion of that interrupt source.
Only used by the host controller.
System Error.
This bit is not used in this implementation and will always be set to 0.
Frame List Rollover.
The Host Controller sets this bit to a 1 when the Frame List Index rolls over from its maximum value to 0.
The exact value at which the rollover occurs depends on the frame list size. For example. If the frame list
size (as programmed in the Frame List Size field of the USBCMD register) is 1024, the Frame Index Register
rolls over every time FRINDEX [13] toggles. Similarly, if the size is 512, the Host Controller sets this bit to
a 1 every time FHINDEX [12] toggles.
Only used by the host controller.
Port Change Detect.
The Host Controller sets this bit to a 1 when on any port a Connect Status occurs, a Port Enable/Disable
Change occurs, or the Force Port Resume bit is set as the result of a J-K transition on the suspended port.
The Device Controller sets this bit to a 1 when the port controller enters the full or high-speed operational
state. When the port controller exits the full or highspeed operation states due to Reset or Suspend events,
the notification mechanisms are the USB Reset Received bit and the DCSuspend bits respectively.
This bit is not EHCI compatible.
HW_USBCTRL_USBSTS field descriptions (continued)
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
Description
Freescale Semiconductor, Inc.