MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 1247

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

Freescale Semiconductor, Inc.
Reset
WORD_LENGTH
COMMAND_
LOCK_CS
CLKGATE
Bit
W
SFTRST
R
RSVD1
RSVD0
MODE
25 24
Field
RUN
31
30
29
28
27
26
23
15
0
14
0
Set to zero for normal operation. When this bit is set to one (default),
then the entire block is held in its reset state. This will not work if the CLKGATE bit is already set to 1.
CLKGATE must be cleared to 0 before issuing a soft reset. Also the GPMICLK must be running for this to
work properly.
0x0
0x1
Set this bit zero for normal operation. Setting this bit to one (default),
gates all of the block level clocks off for miniminizing AC energy consumption.
0x0
0x1
The GPMI is busy running a command whenever this bit is set to 1. The GPMI is idle whenever this bit set
to zero. This can be set to one by a CPU write. In addition, the DMA sets this bit each time a DMA command
has finished its PIO transfer phase.
0x0
0x1
Always write zeros to this field.
For NAND mode: 0= Deassert chip select (CS) after RUN is complete. 1= Continue to assert chip select
(CS) after RUN is complete.
0x0
0x1
Always write zeros to this field.
00= Write mode.
01= Read Mode.
10= Read and Compare Mode (setting sense flop).
11= Wait for Ready.
0x0
0x1
0x2
0x3
0= not support.
1= 8-bit Data Bus mode.
This bit should only 1.
13
0
RUN — Allow GPMI to operate normally.
RESET — Hold GPMI in reset.
RUN — Allow GPMI to operate normally.
NO_CLKS — Do not clock GPMI gates in order to minimize power consumption.
IDLE — The GPMI is idle.
BUSY — The GPMI is busy running a command.
DISABLED — Deassert chip select (CS) after RUN is complete.
ENABLED — Continue to assert chip select (CS) after RUN is complete.
WRITE — Write mode.
READ — Read mode.
READ_AND_COMPARE — Read and Compare mode (setting sense flop).
WAIT_FOR_READY — Wait for Ready mode.
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
12
0
HW_GPMI_CTRL0 field descriptions
11
0
10
0
0
9
XFER_COUNT
0
8
Description
0
7
Chapter 15 General-Purpose Media Interface(GPMI)
0
6
5
0
4
0
0
3
0
2
0
1
1247
0
0