MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 1587

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

25.6.9 Interrupt Masks 2 Register (HW_CAN_IMASK2)
The default value of this register is 0x00000000.
Freescale Semiconductor, Inc.
RWRN_INT
TWRN_INT
FLT_CONF
CRC_ERR
FRM_ERR
BOFF_INT
BIT1_ERR
BIT0_ERR
ACK_ERR
STF_ERR
WAK_INT
RX_WRN
ERR_INT
TX_WRN
RSVD1
RSVD0
31 18
TXRX
Field
IDLE
5 4
17
16
15
14
13
12
11
10
9
8
7
6
3
2
1
0
Reserved .
If theWRN_EN bit in MCR is asserted, the TWRN_INT bit is set when the TX_WRN flag transition from 0 to
1, meaning that the Tx error counter reached
If theWRN_EN bit in MCR is asserted, the RWRN_INT bit is set when the RX_WRN flag transition from 0
to 1, meaning that the Rx error counters reached
This bit indicates when an inconsistency occurs between the transmitted and the received bit in a message.
This bit indicates when an inconsistency occurs between the transmitted and the received bit in a message.
This bit indicates that an Acknowledge Error has been detected by the transmitter node
This bit indicates that a CRC Error has been detected by the receiver node
This bit indicates that a Form Error has been detected by the receiver node
This bit indicates that a Stuffing Error has been detected.
This bit indicates when repetitive errors are occurring during message transmission.
This bit indicates when repetitive errors are occurring during message reception.
This bit indicates when CAN bus is in IDLE state.
This bit indicates if CAN is transmitting or receiving a message when the CAN bus is not in IDLE state.
This 2-bit field indicates the Confinement State of the CAN module
Reserved.
This bit is set when CAN enters Bus Off state
This bit indicates that at least one of the Error Bits (bits 15-10) is set.
When CAN is Stop Mode and a recessive to dominant transition is detected on the CAN bus and if the
WAK_MSK bit in the MCR Register is set, an interrupt is generated to the ARM.
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
HW_CAN_ESR field descriptions
Description
Chapter 25 Controller Area Network (FlexCAN)
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