MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 1609

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

26.3.2.2 IP Protocol Performance Optimization Features
Freescale Semiconductor, Inc.
• Optional forwarding of received pause frames to the user application when operating
• Implements standard flow-control mechanism in full-duplex operation mode
• In half-duplex mode, provides full collision support, including jamming, backoff, and
• Support for VLAN tagged frames according to IEEE 802.1Q
• Programmable MAC address: Insertion on transmit; discards frames with mismatching
• Programmable group of four supplemental MAC addresses that can be used to filter
• Programmable Promiscuous mode support to omit MAC destination address checking
• Multicast and Unicast address filtering on receive based on 64 entries hash table reducing
• Programmable frame maximum length providing support for any standard or proprietary
• Statistics indicators for frame traffic as well as errors (alignment, CRC, length) and
• Simple handshake user application FIFO interface with fully programmable depth and
• 64-Bit Client FIFO interface
• Separate status word available for each received frame on the user interface providing
• Multiple internal loopback options
• MDIO Master interface for PHY device configuration and management with two
• Operates on TCP/IP and UDP/IP and ICMP/IP protocol data or IP header only
• Enables wire-speed processing
in Full Duplex mode
automatic retransmission
destination address on receive (except broadcast and pause frames)
Unicast traffic
on receive
higher layer processing load
frame length
pause frames providing for IEEE 802.3 basic and mandatory Management Information
Database (MIB) package and Remote Network Monitoring (RFC 2819)
threshold levels ensuring data rates of 1Gbps
information such as frame length, frame type, VLAN tag and error information
programmable MDIO base addresses
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
Chapter 26 Ethernet Controller (ENET)
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