MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 1840

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

Programmable Registers
1840
800F_80BC
800F_804C
800F_805C
800F_806C
800F_808C
800F_809C
800F_8034
800F_8040
800F_8044
800F_8048
800F_8050
800F_8054
800F_8058
800F_8060
800F_8064
800F_8068
800F_8080
800F_8084
800F_8088
800F_8090
800F_8094
Absolute
address
(hex)
ENET SWI The VLAN type field value to expect to identify a
VLAN tagged frame. (HW_ENET_SWI_VLAN_TAG_ID)
ENET SWI Port Mirroring configuration.
(HW_ENET_SWI_MIRROR_CONTROL)
ENET SWI Port Mirroring Egress port definitions.
(HW_ENET_SWI_MIRROR_EG_MAP)
ENET SWI Port Mirroring Ingress port definitions.
(HW_ENET_SWI_MIRROR_ING_MAP)
ENET SWI Ingress Source MAC Address for Mirror filtering.
(HW_ENET_SWI_MIRROR_ISRC_0)
ENET SWI Ingress Source MAC Address for Mirror filtering.
(HW_ENET_SWI_MIRROR_ISRC_1)
ENET SWI Ingress Destination MAC Address for Mirror
filtering. (HW_ENET_SWI_MIRROR_IDST_0)
ENET SWI Ingress Destination MAC Address for Mirror
filtering. (HW_ENET_SWI_MIRROR_IDST_1)
ENET SWI Egress Source MAC Address for Mirror filtering.
(HW_ENET_SWI_MIRROR_ESRC_0)
ENET SWI Egress Source MAC Address for Mirror filtering.
(HW_ENET_SWI_MIRROR_ESRC_1)
ENET SWI Egress Destination MAC Address for Mirror
filtering. (HW_ENET_SWI_MIRROR_EDST_0)
ENET SWI Egress Destination MAC Address for Mirror
filtering. (HW_ENET_SWI_MIRROR_EDST_1)
ENET SWI Count Value for Mirror filtering.
(HW_ENET_SWI_MIRROR_CNT)
ENET SWI Memory Manager Status.
(HW_ENET_SWI_OQMGR_STATUS)
ENET SWI Low Memory threshold.
(HW_ENET_SWI_QMGR_MINCELLS)
ENET SWI Statistic providing the lowest number of free cells
reached in memory (HW_ENET_SWI_QMGR_ST_MINCELLS)
ENET SWI Port Congestion status (internal).
(HW_ENET_SWI_QMGR_CONGEST_STAT)
ENET SWI Switch input and output interface status (internal).
(HW_ENET_SWI_QMGR_IFACE_STAT)
ENET SWI Queue weights for each queue.
(HW_ENET_SWI_QM_WEIGHTS)
ENET SWI Define congestion threshold for Port0
backpressure. (HW_ENET_SWI_QMGR_MINCELLSP0)
ENET SWI Enable forced forwarding for a frame processed
from port 0 (HW_ENET_SWI_FORCE_FWD_P0)
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
HW_ENET_SWI memory map (continued)
Register name
(in bits)
Width
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R
Freescale Semiconductor, Inc.
0060_004Ah
Reset value
0000_8100h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0009h
0000_0000h
0000_0000h
0000_0007h
0000_0000h
0000_0009h
0000_0000h
29.9.13/1857
29.9.14/1857
29.9.15/1859
29.9.16/1860
29.9.17/1861
29.9.18/1861
29.9.19/1862
29.9.20/1862
29.9.21/1863
29.9.22/1863
29.9.23/1864
29.9.24/1864
29.9.25/1865
29.9.26/1865
29.9.27/1867
29.9.28/1867
29.9.29/1868
29.9.30/1869
29.9.31/1870
29.9.32/1871
29.9.33/1871
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