MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 140

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

Operation
The coprocessor instruction sequence above enables an internal gating signal. This internal
signal guarantees that write buffers are drained and ensures that the processor is in an idle
state. On execution of the MCR coprocessor instruction, the CPU clock is stopped and the
processor halts on the instruction waiting for an interrupt to occur.
The INTERRUPT_WAIT bit can be thought of as a Wait-for-Interrupt enable bit. Therefore,
it must be set prior to the execution of the MCR instruction. It is recommended that, when
the Wait-for-Interrupt mode is to be used, the INTERRUPT_WAIT bit be set at initialization
time and left on.
With the INTERRUPT_WAIT bit set, after the execution of the MCR WFI command, the
processor halts on the MCR instruction. When an interrupt or FIQ occurs, the MCR
instruction completes and the IRQ or FIQ handler is entered normally. The return link that
is passed to the handler is automatically adjusted by the above MCR instruction, such that
a normal return from an interrupt results in a continuous execution of the instruction
immediately following the MCR. That is, the LR will contain the address of the MCR
instruction plus eight, such that a typical return from an interrupt instruction (for example,
subs pc, LR, 4) will return to the instruction immediately following the MCR (the NOP in
the example above).
Whenever the CPU is stopped because the clock control HW_CLKCTRL_
CPUCLKCTRL_INTERRUPT_WAIT bit is set and the MCR WFI instruction is executed,
the CPU stops until an interrupt occurs. The actual condition that wakes up the CPU is
determined by ORing together all enabled interrupt requests including those that are directed
to the FIQ CPU input. The ICOLL_BUSY output signal from the ICOLL communicates
this information to the clock control. This function does not pass through the normal ICOLL
state machine. It starts the CPU clock as soon as an enabled interrupt arrives.
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2. After setting the INTERRUPT_WAIT bit, a coprocessor instruction is required.
asm (
// Note: R0 is used in the following example, but any usual <Rd> register may be used.
"mov R0, 0;"
"mcr p15,0,r0,c7,c0,4;" //Drain write buffers, idle CPU clock & processor, and stop
"nop");
uclkctrl |= BM_CLKCTRL_CPUCLKCTRL_INTERRUPT_WAIT;
HW_CLKCTRL_CPUCLKCTRL_WR(uclkctrl);
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
// Rd SBZ (should be zero)
//processor at this instruction
// The lr sent to handler points here after RTI
Freescale Semiconductor, Inc.