MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 2225

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

36.2.1 Interrupts
The SPDIF module contains a single interrupt source that is asserted on FIFO overflows
and/or FIFO underflows. This interrupt is enabled by setting
HW_SPDIF_CTRL_FIFO_ERROR_IRQ_EN. On interrupt detection, the
HW_SPDIF_CTRL_FIFO_UNDERFLOW_IRQ and
HW_SPDIF_CTRL_FIFO_OVERFLOW_IRQ fields can be polled for the exact cause of
the interrupt and appropriate action taken.
36.2.2 Clocking
The IEC-60958 specification outlines the requirements for SPDIF clocking. The SPDIF
module is designed according to the Consumer Audio requirements. These dictate that:
The jitter requirement implies either a single-phase of a >240 MHz clock or both phases of
a 120 MHz clock. It also implies the use of a fractional divider for which the divisors are
maintained to sufficient significant digits to yield the required ppm tolerance. The SPDIF
module in the i.MX28 uses nine-bit fractional coefficients that yield an average frequency
error of 52 ppm. These coefficients are determined according to the required clock-rates
that are dictated by the sample rates implemented. The required clock frequencies provided
by the CLKCTRL module for the implemented sample-rates are:
All clocks within the SPDIF module are gated according to the state of
HW_SPDIF_CTRL_CLKGATE. When set, all clocks derived from the apb_clk are gated.
Gating of the pcm_spdif_clk is accomplished through HW_CLKCTRL_SPDIF_CLKGATE.
Freescale Semiconductor, Inc.
• Average Sample-Rate Error must not exceed 1000 ppm
• Maximum Instantaneous Jitter must not exceed ~4.4 ns.
F(48 kHz) 6.144 MHz
F(44.1 kHz) 5.6448 MHz
F(32 kHz) 4.096 MHz
F(96 kHz) 12.288 MHz
F(88.2 kHz) 11.2896 MHz
F(64 kHz) 8.192 MHz
These bits remain valid for polling, regardless of the state of the
interrupt enable.
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
Chapter 36 Sony-Philips Digital Interface Format Transmitter (SPDIF)
Note
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