MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 1988

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

Programmable Registers
1988
RSVD4
RSVD3
RSVD2
RSVD1
23 20
15 11
ULPIE
NAKE
UPIE
UAIE
Field
TIE0
URE
SRE
AAE
SLE
24
19
18
17
16
10
9
8
7
6
5
General-Purpose Timer Interrupt Enable 0.
When this bit is a 1, and the GPTINT0 bit in the USBSTS register is a 1, the controller will issue an interrupt.
The interrupt is acknowledged by software clearing the GPTINT0 bit.
Reserved.
USB Host Periodic Interrupt Enable.
When this bit is a 1, and the USBHSTPERINT bit in the USBSTS register is a 1, the host controller will issue
an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the
USBHSTPERINT bit.
USB Host Asynchronous Interrupt Enable.
RW 0x0 When this bit is a 1, and the USBHSTASYNCINT bit in the USBSTS register is a 1, the host controller
will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the
USBHSTASYNCINT bit.
Reserved.
NAK Interrupt Enable.
This bit is set by software if it wants to enable the hardware interrupt for the NAK Interrupt bit. If both this
bit and the corresponding NAK Interrupt bit are set, a hardware interrupt is generated.
Reserved.
ULPI Enable.
Not used in this implementation.
Reserved.
Sleep Enable.
When this bit is a 1, and the DCSuspend bit in the USBSTS register transitions, the device controller will
issue an interrupt. The interrupt is acknowledged by software writing a 1 to the DCSuspend bit. Only used
by the device controller.
SOF Received Enable.
When this bit is a 1, and the SOF Received bit in the USBSTS register is a 1, the device controller will issue
an interrupt. The interrupt is acknowledged by software clearing the SOF Received bit.
USB Reset Enable.
When this bit is a 1, and the USB Reset Received bit in the USBSTS register is a 1, the device controller
will issue an interrupt. The interrupt is acknowledged by software clearing the USB Reset Received bit. Only
used by the device controller.
Interrupt on Async Advance Enable.
When this bit is a 1, and the Interrupt on Async Advance bit in the USBSTS register is a 1, the host controller
will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the
Interrupt on Async Advance bit. Only used by the host controller.
HW_USBCTRL_USBINTR field descriptions (continued)
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
Description
Freescale Semiconductor, Inc.