MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 1259

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

Chapter 16
20-BIT Correcting ECC Accelerator (BCH)
16.1 BCH Overview
The hardware ECC accelerator provides a forward error-correction function for improving
the reliability of various storage media that may be attached to the device. For example,
modern high-density NAND flash devices presume the existence of forward error-correction
algorithms to correct some soft and/or hard bit errors within the device, allowing for higher
device yields and, therefore, lower NAND device costs.
The Bose, Ray-Chaudhuri, Hocquenghem (BCH) Encoder and Decoder module is capable
of correcting from 2 to 20 single bit errors within a block of data no larger than about 900
bytes (512 bytes is typical) in applications such as protecting data and resources stored on
modern NAND flash devices. The correction level in the BCH block is programmable to
provide flexibility for varying applications and configurations of flash page size. The design
can be programmed to encode protection of 2, 4, 6, 8, 10, 12, 14, 16, 18, or 20 bit errors
when writing flash and to correct the corresponding number of errors on decode. The
correction level when decoding MUST be programmed to the same correction level as was
used during the encode phase.
BCH-codes are a type of block-code, which implies that all error-correction is performed
13
over a block of N-symbols. The BCH operation will be performed over GF(2
= 8192),
which is the Galois Field consisting of 8191 one-bit symbols. BCH-encoding (or encode
for any block-code) can be performed by two algorithms: systematic encoding or
multiplicative encoding. Systematic encoding is the process of reading all the symbols
which constitute a block, dividing continuously these symbols by the generator polynomial
for the GF(8192) and appending the resulting t parity symbols to the block to create a BCH
codeword (where t is the number of correctable bits).
The BCH encode process creates t 13-bit parity symbols for each data block when the data
is written to the flash device. The parity symbols are written to the flash device after the
corresponding data block, and together these are collectively called the codeword. The
codeword can be used during the decode process to correct errors that occur in either the
data or parity blocks.
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
Freescale Semiconductor, Inc.
1259