MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 1890

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

Programmable Registers
29.9.50 ENET SWI Port 0 VLAN priority resolution map
Port 0 VLAN priority resolution map. The 3-bit to 3-bit priority map addressed by the
priority bits of the VLAN tag
The VLAN_PRIORITY0 registers implement a 3-bit to 3-bit VLAN priority mapping
capability. The current frame's 3-bit VLAN priority field is used as an index and the
corresponding priority is taken from the respective position of the register giving the final
classification for the frame.
Address:
Re-
1890
set
Bit
W
R
PROTOCOL
31
RSRVD0
RSRVD0
ENABLE
0
MODE
31 24
Field
15 8
Field
7 3
2 1
30
0
0
29
0
RSRVD0
HW_ENET_SWI_VLAN_PRIORITY0
8100h
(HW_ENET_SWI_VLAN_PRIORITY0)
28
0
The 8-bit protocol value to match with the incoming frame's IP header protocol field.
Reserved bits. Write as 0.
Defines the forwarding that should occur, when an IP frame is received and the protocol field matches the
protocol value (see bits 15:8).
Bits 2:1:
00: forward frame to designated management port only 01: copy to management port and forward normally
10: discard
Note: the management port is defined in register MGMT_CONFIG.
When set (1) the entry contains valid data and the function is active. If a match with the protocol value occurs,
the frame is processed as defined by the mode setting.
All other bits of the register are interpreted by the IP snooping function only if the enable bit is set. Otherwise
the settings are ignored.
Defaults to 0 upon reset.
Reserved bits. Write as 0.
27
0
HW_ENET_SWI_IPSNOOP8 field descriptions (continued)
26
0
HW_ENET_SWI_VLAN_PRIORITY0 field descriptions
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
25
0
24
0
23
0
P7
22
0
21
0
20
0
P6
19
0
18
800F_8000h base + 100h offset = 800F_
0
17
0
P5
16
0
15
0
Description
Description
14
0
P4
13
0
12
0
11
0
P3
10
0
0
9
0
8
Freescale Semiconductor, Inc.
P2
0
7
0
6
0
5
P1
0
4
3
0
0
2
P0
0
1
0
0