MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 2129

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

34.2.8 Raster Operations (ROPs)
In addition to alpha blending and color keying, the PXP's alpha blender also supports a set
of raster operations that may be performed between the active overlay and the background
image. The operations are done on a per-pixel basis and are performed using the 24-bit
overlay and background image values. The following table lists the supported ROP operations
These operations are specified in the overlay's PARAM register and must be enabled by
setting the ALPHA_CTRL field to ROPs.
34.2.9 Rotation
Rotation is an inherently inefficient operation, especially for a graphics device operating
in a raster-scan fashion since the resulting memory fetches would be non-contiguous. The
PXP solves this problem by operating on NxN pixel blocks. This allows the PXP to rotate
a subportion of the image, where it can fetch N lines of pixels, process them, and then write
N lines of pixels regardless of the rotation orientation.
Freescale Semiconductor, Inc.
MERGEOLNOT
NOTMERGEOL
MERGEOLNET
MASKNOTOL
MASKOLNOT
NOTCOPYOL
NOTMASKOL
NOTXOROL
MERGEOL
Mnemonic
MASKOL
XOROL
NOT
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
Table 34-2. Supported ROP Operations
Value
0xA
0xB
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
0x8
0x9
Chapter 34 Pixel Pipeline (PXP)
~(OL & S0) (nand)
~(OL ^ S0) (xnor)
~(OL | S0) (nor)
OL ^ S0 (xor)
OLL & ~S0
Operation
~OL & S0
~OL | S0
OL | ~S0
OL & S0
OL | S0
~OL
~S0
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