MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 1798

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

Programmable Registers
HW_PWM_PERIOD5_TOG: 0x0cC
EXAMPLE
HW_PWM_PERIODn_WR(5, 0x00000b1f);
Address:
1798
Reset
Reset
HSADC_CLK_
HSADC_OUT
MATT_SEL
Bit
Bit
W
W
RSRVD2
R
R
31 27
22 20
MATT
CDIV
Field
SEL
26
25
24
23
31
15
0
0
HW_PWM_PERIOD5
30
14
0
0
Reserved.
PWM output to HSADC.Setting this bit to 1'b1, output of PWM channel 5 is routed to HSADC internally.Only
one PWM channle's HSADC_OUT should be set to 1'b1.
If multiple PWM channels are set as HSADC_OUT, only the channel with the lowest channel number will
be routed to HSADC
HSADC clock select for PWM output. Setting this bit to 1'b1, PWM channel 5 counts on HSADC input clock
to drive PWM output.
Multichip Attachment Mode clock select. When the MATT bit is asserted this bit selects which clock to output.
0: 32 kHz, 1: 24 MHz.
Multichip Attachment Mode. This bit overrides the normal signal generation parameters and enables either
the 24 MHz or 32 kHz crystal clock on the PWM5 output pin for inter-chip signaling.
When this bit is set to 0x1, bit HSADC_CLK_SET in Period Register must be set to 0x0. Otherwise, something
unexpected may happen.
Clock divider ratio to apply to the crystal/HSADC clock frequency that times the PWM output signal.
0x0
0x1
0x2
0x3
0x4
0x5
RSRVD2
29
13
0
0
DIV_1 — Divide by 1.
DIV_2 — Divide by 2.
DIV_4 — Divide by 4.
DIV_8 — Divide by 8.
DIV_16 — Divide by 16.
DIV_64 — Divide by 64.
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
28
12
0
0
HW_PWM_PERIOD5 field descriptions
8006_4000h base + C0h offset = 8006_40C0h
27
11
0
0
26
10
0
0
// Set up period and active/inactive output states
25
0
0
9
24
0
0
8
PERIOD
Description
23
0
0
7
22
0
0
6
CDIV
21
0
5
0
20
0
4
0
Freescale Semiconductor, Inc.
INACTIVE_
19
0
0
3
STATE
18
0
0
2
17
ACTIVE_
0
0
1
STATE
16
0
0
0