MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 1067

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

Command handling is summarized in the following table.
Freescale Semiconductor, Inc.
Two Read Commands from 1 port
Two Read Commands from 1 port
Two Read Commands from Different ports
Two Write Commands from 1 port
Two Write Commands from 1 port
Two Write Commands from Different ports
Read/Write or Write/Read Command from 1 port
Read/Write or Write/Read Command from 1 port
Read/Write or Write/Read Command from Different ports
Commands
• For the AHB-bridged ports, read commands will always execute in the same order as
• For the native AXI ports, read commands from the same thread ID will always execute
• For the native AXI ports, write commands from the same or different thread IDs will
• Read or Write commands from different AHB-bridged or native AXI ports may be
• Within an AHB-bridged port, a write command that is accepted into the port after a
• Within a native AXI port, read and write commands from the same or different thread
they were accepted into the port. Similarly, write commands will always execute in the
same order as they were accepted into the port.
in the same order as they were accepted into the port. However, read commands from
different thread IDs on the native AXI ports may be automatically re-arranged in the
core logic to execute out-of-order. When commands from different thread IDs are
re-ordered, read data returned to the AXI port interfaces will also be out-of-order and
may be interleaved. To avoid re-ordering within a port, the AXI bus master should use
one thread ID for all commands from any port.
always execute in the same order as they were accepted into the port.
automatically re-arranged in the EMI to execute out-of-order.
read will not be executed ahead of the read command. However, a read command that
is accepted into the port after a write may be indeterminably re-arranged in the EMI
ahead of the write command.
IDs may be re-arranged in the core logic. Read and write commands with different
thread IDs will be automatically re-arranged to execute in an optimal order, as long as
there are no collisions between the commands.
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
Table 14-1. Reordering/Interleaving Behavior
Same or Different
Same or Different
Same or Different
Thread ID
Different
Different
Different
Same
Same
Same
Can Commands be Rearranged and Data be
Chapter 14 External Memory Interface (EMI)
Interleaved?
Maybe
Yes
No
Yes
Yes
Yes
Yes
No
No
1
1
1
2
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