MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 1009

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

To minimize the number of registers used in the design, the controller saves context
information from each channel into a private context area in the system memory. When
initializing the DCP module, software must allocate memory for the context buffer and
write the address into the Context Buffer Pointer register. As the DCP module processes
packets, it saves the context information for each channel to the buffer after completing
each control packet. When the channel is subsequently activated, the DCP module's internal
registers are then reloaded with the proper context before resuming the operation.
Each channel reserves one-fourth of the context buffer area for its context storage. The
context buffer consumes 208 bytes of system memory and is formatted as shown in the
following table.
The control logic writes to the context buffer only if the function is being used. This
effectively means that the cipher context is stored for CBC encryption/decryption operations
only and the hash context is written only if SHA-1/SHA-256 is utilized. If neither of these
modes are used for a given channel, the memory for the context buffer need not be allocated
by the software.
Since channel 0 is likely to be used for VMI in an SDRAM-based system-to-page data from
the SDRAM to on-chip SRAM, the buffer allocation table has been organized so that the
highest numbered channel uses the lowest area in the context buffer. For this reason, software
should allocate the higher numbered channels for encryption/hashing operations and the
lower numbered channels for memcopy operations to reduce the size of the context buffer.
If only a single channel is used for CBC mode operations or hashing operations, the controller
provides a bit in the control register to disable context switching. In this scenario, context
switching is not required, because other channels will not corrupt the state of the hashing
or cipher modes. Therefore, when the channel resumes, a context load is not required.
Freescale Semiconductor, Inc.
0xAC 0xCC
0x9C 0xA8
0x00 0x0C
0x10 0x30
0x34 0x40
0x44 0x64
0x68 0x74
0x78 0x98
RANGE
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
Table 13-1. DCP Context Buffer Layout
Channel
3
2
1
0
Cipher Context
Cipher Context
Cipher Context
Cipher Context
Hash Context
Hash Context
Hash Context
Hash Context
Data
Chapter 13 Data Co-Processor (DCP)
16 bytes
36 bytes
16 bytes
36 bytes
16 bytes
36 bytes
16 bytes
36 bytes
Size
1009