MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 1052

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

Programmable Registers
13.3.27 DCP Channel 2 Options Register (HW_DCP_CH2OPTS)
The DCP Channel 2 Options Status register contains optional control information that may
be used to further tune the behavior of the channel.
HW_DCP_CH2OPTS: 0x1B0
HW_DCP_CH2OPTS_SET: 0x1B4
HW_DCP_CH2OPTS_CLR: 0x1B8
HW_DCP_CH2OPTS_TOG: 0x1BC
The options register can be used to control optional features of the channels.
Address:
Re-
1052
set
Bit
ERROR_SETUP
W
R
ERROR_DST
ERROR_SRC
COMPLETE
MISMATCH
ERROR_
31
PACKET
0
HASH_
RSVD_
Field
30
5
4
3
2
1
0
0
29
0
HW_DCP_CH2OPTS
28
0
This bit indicates a bus error occurred when storing to the destination buffer. When an error is detected, the
channel's processing will stop until the error handled by software.
This bit indicates a bus error occurred when reading from the source buffer. When an error is detected, the
channel's processing will stop until the error handled by software.
This bit indicates that a bus error occurred when reading the packet or payload or when writing status back
to the packet paylaod. When an error is detected, the channel's processing will stop until the error is handled
by software.
This bit indicates that the hardware detected an invalid programming configuration such as a buffer length
that is not a multiple of the natural data size for the operation. When an error is detected, the channel's
processing will stop until the error is handled by software.
The bit indicates that a hashing check operation mismatched for control packets that enable the
HASH_CHECK bit. When an error is detected, the channel's processing will stop until the error is handled
by software.
This bit will always read 0 in the status register, but will be set to 1 in the packet status field after processing
of the packet has completed. This was done so that software can verify that each packet completed properly
in a chain of commands for cases when an interrupt is issued only for the last item in a packet. The completion
bit for the channel is effectively the channel interrupt status bit.
27
0
26
0
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
HW_DCP_CH2STAT field descriptions (continued)
25
0
RSVD
24
0
23
0
22
8002_8000h base + 1B0h offset = 8002_81B0h
0
21
0
20
0
19
0
18
0
17
0
16
0
15
0
Description
14
0
13
0
12
0
11
0
10
RECOVERY_TIMER
0
0
9
0
8
Freescale Semiconductor, Inc.
0
7
0
6
0
5
0
4
3
0
0
2
0
1
0
0