MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 1075

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

14.4.8.4 Read Commands to Exclusive Access Regions
A memory area is not locked while an exclusive access is valid and therefore other source
IDs may issue read commands to a memory area identified as exclusive. Reads, even other
exclusive reads, do not affect the exclusivity of a region. Normal read commands will be
processed as usual and, if successful, respond to the master with an OKAY (‘b00) on the
axi_RRESP signal. Exclusive read commands will result in additional entries being created
in the exclusive access buffers and, if successful, an EXOKAY (‘b01) response will be sent
on the axi_RRESP signal.
Note: An exclusive read request from any source ID, from the same port or another port,
even to an overlapping address within an exclusive access region, will not affect the initial
exclusive access. Another entry will be created in that port’s buffer for this request.
14.4.8.5 Non-Exclusive Write Commands to Exclusive Access Regions
Any master in the system may issue a write command to a memory area identified as
exclusive. However, a standard write to any address within an active exclusive access region
will invalidate the exclusivity of that region. In this case, the “valid” bit of any exclusive
access buffer entry that spans the modified locations in memory will be cleared and future
exclusive write requests to this region will fail their exclusivity check.
14.4.8.6 Exclusive Writes
An exclusive write command is only distinguished from a standard write command by the
axi_AWLOCK signal being driven to ‘b01. When an exclusive write is received, the EMI
first compares the source ID (axi_AWID and port number), transaction beat length
(axi_AWLEN), transaction start address (axi_AWADDR), and transaction beat size
(axi_AWSIZE) to the entries in the exclusive access buffer of that port.
Freescale Semiconductor, Inc.
• The user is tracking enough exclusive access commands that the exclusive access buffer
• The same source ID issues another exclusive read request for another memory region.
for this port is full. Newer commands will be stored, overriding a previous exclusive
access entry.
This will not clear the valid bit, but will actually overwrite the entire exclusive access
buffer entry (and then set the valid bit). The EMI will only track one exclusive region
for each source ID.
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
Chapter 14 External Memory Interface (EMI)
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