MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 1589

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

This register defines the flags for 32 message buffer interrupts. It contains one interrupt
flag bit per buffer. Each successful transmission or reception sets the corresponding IFLAG2
bit. If the corresponding IMASK2 bit is set, an interrupt is generated. The interrupt flag
must be cleared by writing a 1; writing 0 has no effect. When the AEN bit in the MCR is
set (abort enabled), while the IFLAG2 bit is set for a message buffer configured as Tx,
ARM write access to the corresponding message buffer is blocked.
Address:
Re-
25.6.12 Interrupt Flags 1 Register (HW_CAN_IFLAG1)
The default value of this register is 0x00000000.
This register defines the flags for 32 message buffer interrupts and FIFO interrupts. It
contains one interrupt flag bit per buffer. Each successful transmission or reception sets the
corresponding IFLAG1 bit. If the corresponding IMASK1 bit is set, an interrupt is generated.
The interrupt flag must be cleared by writing a 1 to it. Writing 0 has no effect. Setting the
abort enabled (AEN) bit in the MCR while the IFLAG1 bit is set for a message buffer
configured as Tx blocks the ARMs write access to the corresponding message buffer. Setting
the FIFO enable (FEN) bit in the MCR changes the function of the 8 least significant interrupt
flags (BUF7ICBUF0I) to support the FIFOs operation. BUF7I, BUF6I, and BUF5I indicate
operating conditions of the FIFO; BUF4ICBUF0I are not used.
Address:
Re-
Freescale Semiconductor, Inc.
set
set
Bit
Bit
W
W
R
R
31
31
0
0
BUFI
Field
31 0
30
30
0
0
29
29
0
0
HW_CAN_IFLAG2
HW_CAN_IFLAG1
28
28
0
0
This register defines the flags for 32Message Buffer interrupts.
27
27
0
0
26
26
0
0
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
25
25
0
0
24
24
0
0
23
23
0
0
8003_2000h base + 2Ch offset = 8003_202Ch
8003_2000h base + 30h offset = 8003_2030h
HW_CAN_IFLAG2 field descriptions
22
22
0
0
21
21
0
0
20
20
0
0
19
19
0
0
18
18
0
0
17
17
0
0
16
16
0
0
BUFI
BUFI
15
15
0
0
Description
14
14
0
0
13
13
0
0
Chapter 25 Controller Area Network (FlexCAN)
12
12
0
0
11
11
0
0
10
10
0
0
0
0
9
9
0
0
8
8
0
0
7
7
0
0
6
6
0
0
5
5
0
0
4
4
3
0
3
0
0
0
2
2
0
0
1
1
1589
0
0
0
0