MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 1535

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

24.3.2 UART Receive Status Register (Read) / Error Clear Register
The RSR_ECR register is the receive status register/error clear register. Receive status can
also be read from RSR_ECR. If the status is read from this register, then the status
information for break, framing and parity corresponds to the data character read from DR
prior to reading RSR_ECR. The status information for overrun is set immediately when an
overrun condition occurs. A write to RSR_ECR clears the framing, parity, break, and overrun
errors.
Address:
Re-
Freescale Semiconductor, Inc.
set
Bit
W
R
UNAVAILABLE
31
0
DATA
Field
Field
31 8
7 0
7 4
OE
BE
PE
EC
FE
10
30
9
8
3
0
29
0
(Write) (HW_UARTDBG_ECR)
HW_UARTDBG_ECR
28
0
Break Error. This bit is set to 1 if a break condition was detected, indicating that the received data input was
held LOW for longer than a full-word transmission time (defined as start, data, parity and stop bits). In FIFO
mode, this error is associated with the character at the top of the FIFO. When a break occurs, only one 0
character is loaded into the FIFO. The next character is only enabled after the receive data input goes to a
1 (marking state), and the next valid start bit is received.
Parity Error. When this bit is set to 1, it indicates that the parity of the received data character does not match
the parity selected as defined by bits 2 and 7 of the LCR_H register. In FIFO mode, this error is associated
with the character at the top of the FIFO.
Framing Error. When this bit is set to 1, it indicates that the received character did not have a valid stop bit
(a valid stop bit is 1). In FIFO mode, this error is associated with the character at the top of the FIFO.
Receive (read) data character. Transmit (write) data character.
The UART IP only implements 16 and 8-bit registers, so the top 2 or 3 bytes of every 32-bit register are
always unavailable.
Error Clear. Any write to this bitfield clears the framing, parity, break, and overrun errors. The value is
unpredictable when read.
Overrun Error. This bit is set to 1 if data is received and the FIFO is already full. This bit is cleared to 0 by
any write to RSR_ECR. The FIFO contents remain valid since no further data is written when the FIFO is
full, only the contents of the shift register are overwritten. The CPU must now read the data in order to empty
the FIFO.
27
0
26
0
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
25
HW_UARTDBG_DR field descriptions (continued)
0
24
0
23
HW_UARTDBG_ECR field descriptions
0
22
0
8007_4000h base + 4h offset = 8007_4004h
UNAVAILABLE
21
0
20
0
19
0
18
0
17
0
16
0
15
0
Description
Description
14
0
13
0
12
0
11
0
10
0
0
9
Chapter 24 Debug UART (DUART)
0
8
0
7
0
6
EC
0
5
0
4
3
0
0
2
0
1
1535
0
0