MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 888

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

Programmable Registers
Address:
888
Reset
Reset
CLKGATEHSADC
HSADC_STABLE
CLKGATEGPMI
GPMI_STABLE
HSADCFRAC
CLKGATEPIX
GPMIFRAC
Bit
Bit
W
W
R
R
RSRVD2
31 24
21 16
13 8
Field
23
22
15
14
7
31
15
0
1
HW_CLKCTRL_FRAC1
30
14
0
0
Always set to zero (0).
GPMI Clock Gate. If set to 1, the GPMI fractional divider clock (reference PLL0 ref_gpmi) is off (power
savings). 0: GPMI fractional divider clock is enabled.
This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become
stable quickly enough that this field will never need to be used by either device driver or application code.
The value inverts when the new programmed fractional divide value has taken effect. Read this bit, program
the new value, and when this bit inverts, the phase divider clock output is stable. Note that the value will
not invert when the fractional divider is taken out of or placed into clock-gated state.
This field controls the GPMI clock fractional divider. The resulting frequency shall be 480 * (18/GPMIFRAC)
where GPMIFRAC = 18-35.
HSADC Clock Gate. If set to 1, the HSADC fractional divider clock (reference PLL0 ref_adc) is off (power
savings). 0: HSADC fractional divider clock is enabled.
This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become
stable quickly enough that this field will never need to be used by either device driver or application code.
The value inverts when the new programmed fractional divide value has taken effect. Read this bit, program
the new value, and when this bit inverts, the phase divider clock output is stable. Note that the value will
not invert when the fractional divider is taken out of or placed into clock-gated state.
This field controls the HSADC clock fractional divider. The resulting frequency shall be 480 *
(18/HSADCFRAC) where HSADCFRAC = 18-35.
PIX Clock Gate. If set to 1, the PIX fractional divider clock (reference PLL0 ref_pix) is off (power savings).
0: PIX fractional divider clock is enabled.
29
13
0
0
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
28
12
RSRVD2
0
1
HW_CLKCTRL_FRAC1 field descriptions
HSADCFRAC
27
11
0
0
8004_0000h base + 1C0h offset = 8004_01C0h
26
10
0
0
25
0
1
9
24
0
0
8
Description
23
1
1
7
22
0
0
6
21
0
5
0
20
1
4
1
Freescale Semiconductor, Inc.
GPMIFRAC
PIXFRAC
19
0
0
3
18
0
0
2
17
1
1
1
16
0
0
0