MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 1077

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

Chapter 14 External Memory Interface (EMI)
14.4.9.2 AXI Error Reporting
If an AXI command error occurs, a bit will be set in the int_status parameter and the address
and source ID of the command are saved in the port_cmd_error_addr and port_cmd_error_id
parameters, respectively. In addition, the access type that relate to the error are stored in
the port_cmd_error_type parameter.
Similarly, when a data error occurs, the source ID of the command is saved in the
port_data_error_id parameter. The access type that relate to the error are stored in the
port_data_error_type parameter.
The bits in the error type parameters are not exclusive. Multiple bits may be set to indicate
the type of errors that occurred. Reading the int_ack parameter will allow future errors to
be captured in these error parameters.
If multiple errors occur prior to an acknowledgment of the first error, the parameters will
still represent the first error attributes. Other error signatures will be lost. If multiple errors
occur simultaneously on different ports, the error information will represent the lowest
numbered erring port.
14.4.10 Arbiter
From the port interface blocks, commands are presented to the Arbiter, which is responsible
for arbitrating between the port requests and sending a single command to the core logic.
Refer to the “EMI Multi-Port Arbiter” Chapter for details.
14.4.11 Write Data Queue
The write data queue is a write data storage array for transactions. The queue consists of
multiple buffers holding write data for the write requests of a particular port. Write data is
stored in these buffers for commands in the command queue until the command is processed
in the placement logic and needed by the DRAM command arbitration logic. The buffers
can accept data whenever any space is available.
14.4.12 DRAM Command Processing
The DRAM command processing logic is used to process the commands in the Command
Queue. The logic organizes the commands to the memory devices in such a way that data
throughput is maximized. DRAM-Bank opening and closing cycles are used for data
transfers.
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
Freescale Semiconductor, Inc.
1077