MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 1417

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

Address:
Re-
19.4.63 Default First-Level Page Table Movable PTE Locator 13
This register is used by the DFLPT to set the location for MPTE13.
When using the hardware-based Default First-Level Page Table (DFLPT), program this
value to set the location for Movable PTE (MPTE13) to any of the 4096 sections.
Address:
Re-
Freescale Semiconductor, Inc.
set
set
Bit
Bit
W
W
R
R
31
31
0
0
RSVD1
RSVD0
30 27
26 24
23 12
SPAN
Field
11 0
LOC
DIS
31
30
30
0
0
RSVD1
RSVD1
29
29
0
0
HW_DIGCTL_MPTE12_LOC
HW_DIGCTL_MPTE13_LOC
(HW_DIGCTL_MPTE13_LOC)
28
28
0
0
Setting this bit to 1 disables the MPTE. A disabled MPTE cannot be bound to the page table and cannot be
modified.
Reserved.
This bit-field allows this PTE to span a larger than 1MB section of memory. Specifically 1MB * (2^SPAN).
Care must be taken to make sure that spanned regions do not overlap in the page table, since the DFLPT
does not provide any correction mechanism in an overlapped scenario. Because only one value can be set
for the MPTE base-address section entry, the DFLPT assumes linear physical 1 MB addressing within a
SPAN. For example, assuming a value N for LOC and SPAN=2, the DFLPT assumes the value of LOC,
LOC+1, LOC+2 and LOC+3 for the four values within that span; that is, all base addresses within a span
are contiguous.
Reserved.
Value of LOC corresponds to 1MB section number (0x000-0xFFF) within the DFLPT.Note that when the
SPAN field is used, any MPTE can cover up to 128MB. Do not program to 0x800 (fixed PIO entry). No two
HW_DIGCTL_MPTEn_LOC registers can have the same value, and care must be taken to not create overlap
when using the SPAN feature. Doing so will result in non-deterministic behavior of the DFLPT.
27
27
0
0
26
26
0
0
SPAN
SPAN
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
25
25
0
0
HW_DIGCTL_MPTE12_LOC field descriptions
24
24
0
0
23
23
0
0
22
22
0
0
21
21
0
0
20
20
8001_C000h base + 5C0h offset = 8001_C5C0h
8001_C000h base + 5D0h offset = 8001_C5D0h
0
0
19
19
0
0
RSVD0
RSVD0
18
18
0
0
17
17
0
0
16
16
0
0
15
15
0
0
Description
Chapter 19 Digital Control (DIGCTL) and On-Chip RAM
14
14
0
0
13
13
0
0
12
12
0
0
11
11
0
0
10
10
0
0
0
0
9
9
0
0
8
8
0
0
7
7
0
0
6
LOC
6
LOC
0
0
5
5
0
0
4
4
3
1
3
1
1
1
2
2
0
0
1
1
1417
0
1
0
0