MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 1542

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

Programmable Registers
24.3.10 UART Interrupt Mask Set/Clear Register (HW_UARTDBG_IMSC)
The IMSC register is the Interrupt Mask Set/Clear Register. On a read, this register gives
the current value of the mask on the relevant interrupt. On a write of 1 to the particular bit,
it sets the corresponding mask of that interrupt. A write of 0 clears the corresponding mask.
Special Note: Here Mask means Enable.Mask=1 means that bit interrupt is enabled
Address:
1542
Reset
Reset
UNAVAILABLE
Bit
Bit
Reserved
W
W
R
R
31 16
15 11
OEIM
BEIM
PEIM
Field
Field
10
9
8
31
15
0
0
HW_UARTDBG_IMSC
30
14
0
0
0x2
0x3
0x4
0x5
0x6
0x7
The UART IP only implements 16 and 8-bit registers, so the top 2 or 3 bytes of every 32-bit register are
always unavailable.
This bitfield is reserved.
Reserved, do not modify, read as zero.
Overrun Error Interrupt Mask. On a read, the current mask for the OEIM interrupt is returned. On a write of
1, the mask of the OEIM interrupt is set. A write of 0 clears the mask.
Break Error Interrupt Mask.
Parity Error Interrupt Mask.
RESERVED
29
13
0
0
ONE_HALF — Trigger when FIFO becomes equal or less than one-half full.
THREE_QUARTERS — Trigger when FIFO becomes equal or less than three-quarters full.
SEVEN_EIGHTHS — Trigger when FIFO becomes equal or less than seven-eights full.
INVALID5 — Reserved.
INVALID6 — Reserved.
INVALID7 — Reserved.
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
HW_UARTDBG_IFLS field descriptions (continued)
28
12
0
0
HW_UARTDBG_IMSC field descriptions
27
11
8007_4000h base + 38h offset = 8007_4038h
0
0
OEIM
26
10
0
0
BEIM
25
0
0
9
UNAVAILABLE
PEIM
24
0
0
8
Description
Description
FEIM
23
0
0
7
RTIM
22
0
0
6
TXIM
21
0
5
0
RXIM
20
0
4
0
Freescale Semiconductor, Inc.
19
0
0
3
18
0
0
2
17
0
0
1
16
0
0
0