MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 1456

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

Programmable Registers
1456
ENABLE_ARM_
MMU_DISABLE
ENABLE_SSP_
HAB_DISABLE
BOOT_CHECK
ENABLE_PIN_
HAB_CONFIG
RESET_USB_
BOOT_MODE
12MA_DRIVE
RECOVERY_
RECOVERY_
ARM_PLL_
I2C_USE_
STARTUP
PHY_AT_
DISABLE
DISABLE
RSRVD2
FORCE_
RSRVD1
RSRVD0
ICACHE
400KHZ
31 24
21 20
19 12
Field
7 4
23
22
11
10
9
8
3
2
1
0
Reserved - do not blow these bits.
0 - Force Recovery Enable
1 - Force Recovery Disable
0 - Not disabled : ARM core will run at 240MHz for high speed boot
1 - Disabled : ARM core will run at xtal 24MHz for boot
00 - HAB_FAB : Blank out of FAB
01 - HAB_OPEN : For non-secure shipping products, or secure products under development., the ROM will
boot the image even if the HAB authentication fails.
Other - HAB_CLOSED : For the end product, the ROM will not boot unless the image passes the HAB
authentication.
If USB is not desirable for recovery boot mode then these bits can be blown to have the ROM boot from a
non-USB device in recovery mode.
0 - HAB is enabled in default
1 - HAB is disabled
Reserved - do not blow these bits.
Blow to reset the USBPHY at startup This bit will be listed as Reserved in the Data Sheet.
Blow to force SSP pins to drive 12mA, default is 4mA.
Reserved - do not blow these bits.
Blow to force the I2C to be programmed by the boot loader to run at 400KHz, 100KHz is the default.
Blow to enable the ARM 926 ICache during boot.
0 - MMU and D-Cache are enabled during boot.
1 - MMU and D-Cache are disabled during boot.
Blow to enable boot loader to first test the LCD_RS pin to determine if pin boot mode is enabled. If this bit
is blown, and LCD_RS is pulled high, then boot mode is determined by the state of LCD_D[5:0] pins. If this
bit is not blown, skip testing the LCD_RS pin and go directly to determining boot mode by reading the state
of LCD_D[5:0].
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
HW_OCOTP_ROM7 field descriptions
Description
Freescale Semiconductor, Inc.