MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 1525

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

Freescale Semiconductor, Inc.
MATCH_MODE
DUTY_CYCLE
DUTY_VALID
PRESCALE
POLARITY
RSRVD1
RELOAD
UPDATE
IRQ_EN
13 12
Field
IRQ
5 4
15
14
11
10
9
8
7
6
0x2
0x3
0x4
0x5
0x6
0x7
0x8
0x9
0xA
0xB
0xC
0xD
0xE
0xF
This bit is set to one when Timer 3 decrements to zero. Write a zero to clear it or use Clear SCT mode.
Set this bit to one to enable the generation of a CPU interrupt when the count reaches zero in normal counter
mode.
Always write zeroes to this bit field.
Set this bit to one to enable timer match mode
This bit is set and cleared by the hardware. It is set only when in duty cycle measuring mode and the
HW_TIMROT_TIMCOUNT3 has valid duty cycle data to be read. This register will be cleared if not in duty
cycle mode or on writes to this register. In the case that it is written while in duty cycle mode, this bit will
clear but will again be set at the appropriate time for reading the count register.
Set this bit to one to cause the timer to operate in duty cycle measuring mode.
Set this bit to one to invert the input to the edge detector.
0: Positive edge detection.
1: Invert to negative edge detection.
Set this bit to one to cause the running count to be written from the CPU at the same time a new fixed count
register value is written.
Set this bit to one to cause the timer to reload its current count from its fixed count value whenever the
current count decrements to zero. When set to zero, the timer enters a mode that freezes at a count of zero.
When the fixed count is zero, setting this bit to one causes a continuous reload of the fixed count register
so that writting a non-zero value will start the timer.
Selects the divisor used for clock generation. The APBX clock is divided by the following amount. Note the
APBX clock itself is initially divided down from the 24.0-MHz crystal clock frequency.
0x0
0x1
0x2
HW_TIMROT_TIMCTRL3 field descriptions (continued)
DIV_BY_1 — PreScale: Divide the APBX clock by 1.
DIV_BY_2 — PreScale: Divide the APBX clock by 2.
DIV_BY_4 — PreScale: Divide the APBX clock by 4.
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
PWM1 — Input from PWM1.
PWM2 — Input from PWM2.
PWM3 — Input from PWM3.
PWM4 — Input from PWM4.
PWM5 — Input from PWM5.
PWM6 — Input from PWM6.
PWM7 — Input from PWM7.
ROTARYA — Input from Rotary A.
ROTARYB — Input from Rotary B.
32KHZ_XTAL — Input from 32-kHz crystal.
8KHZ_XTAL — Input from 8-kHz (divided from 32-kHz crystal).
4KHZ_XTAL — Input from 4-kHz (divided from 32-kHz crystal).
1KHZ_XTAL — Input from 1-kHz (divided from 32-kHz crystal).
TICK_ALWAYS — Always tick.
Description
Chapter 23 Timers and Rotary Decoder (TIMROT)
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