MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 2068

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

Operation
33.2.4 LCDIF Interrupts
LCDIF supports a number of interrupts to aid controlling and status reporting of the block.
All the interrupts have individual mask bits for enabling or disabling each of them. They
all get funneled through a single interrupt line connected to the interrupt collector (ICOLL).
The following list describes the different interrupts supported by LCDIF:
33.2.5 Initializing the LCDIF
This section describes write modes and MPU read mode
33.2.5.1 Write Modes
The following initialization steps are common to all LCDIF write modes of operation before
entering any particular mode.
Initialization steps:
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1. To select the pins and their directions for talking to the LCD panel, set the appropriate
2. Start the CLK_DIS_LCDIFn clock and set the appropriate frequency by programming
3. Start the HCLK and set the appropriate frequency by programming the registers in
4. Bring the LCDIF out of soft reset and clock gate.
• Underflow interrupt is asserted when the clock domain crossing FIFO (TXFIFO)
• In the bus master mode, the overflow interrupt will be asserted if the block has requested
• VSYNC edge interrupt will be asserted every time a leading VSYNC edge occurs.
• Cur_frame_done interrupt occurs at the end of every frame in all modes except DVI.
becomes empty but the block is in active display portion during that time. Software
should take corrective action to make sure that this does not happen.
more data than it's FIFOs could hold. In the read mode, it will be asserted if the RxFIFO
becomes full and the block reads more data.
In DVI mode, if IRQ_ON_ALTERNATE_FIELDS bit is set, it will occur at the end
of every frame, otherwise it will occur at the end of every field.
bits in the HW_PINCTRL_MUXSELx registers in the PINCTRL block.
the registers in CLKCTRL.
CLKCTRL.
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
Freescale Semiconductor, Inc.